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nxp,kinetis-pinctrl

Vendor: NXP Semiconductors

Description

Kinetis pinctrl node. This node will define pin configurations in pin groups,
and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
within the pin configuration defines the pin configuration for a peripheral,
and each numbered subgroup in the pin group defines all the pins for that
peripheral with the same configuration properties. The 'pins' property in
a group selects the pins to be configured, and the remaining properties set
configuration values for those pins. Here is an example group for UART0 pins:

uart0_default: uart0_default {
  group0 {
    pins = <UART0_RX_PTB16
      UART0_TX_PTB17>;
    drive-strength = "low";
    slew-rate = "fast";
    };
};

If only the required properties are supplied, the pin configuration register
will be assigned the following values:
PCR_PS=0,
PCR_PE=0,
PCR_ODE=0,
PCR_SRE=<slew-rate selection>,
PCR_DSE=<drive-strength selection>,
PCR_PFE=0

Properties

Top level properties

These property descriptions apply to “nxp,kinetis-pinctrl” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Grandchild node properties

Name

Type

Details

pinmux

array

Pin mux selections for this group. See the soc level pinctrl DTSI file
in NXP's HAL for a defined list of these options

This property is required.

drive-strength

string

Pin output drive strength. Sets the DSE field in the PORTx_PCRn register.
0 DSE_0- low drive strength when pin is configured as output
1 DSE_1- high drive strength when pin is configured as output

This property is required.

Legal values: 'low', 'high'

slew-rate

string

Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
0 SRE_0_fast- fast slew rate when pin is configured as output
1 SRE_1_slow- slow slew rate when pin is configured as output

This property is required.

Legal values: 'fast', 'slow'

nxp,passive-filter

boolean

Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.

bias-pull-up

boolean

enable pull-up resistor

bias-pull-down

boolean

enable pull-down resistor

drive-open-drain

boolean

drive with open drain (hardware AND)