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st,lis2dw12 (on i2c bus)

Vendor: STMicroelectronics


STMicroelectronics LIS2DW12 3-axis accelerometer


Properties not inherited from the base binding file.






GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.



Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.



DRDY pin

This pin defaults to active high when produced by the sensor.
The property value should ensure the flags properly describe
the signal that is presented to the driver.



Select DRDY pin number (1 or 2).

   1 # drdy is generated from INT1
   2 # drdy is generated from INT2

This number represents which of the two interrupt pins
(INT1 or INT2) the drdy line is attached to. This property is not
mandatory and if not present it defaults to 1 which is the
configuration at power-up.

Default value: 1

Legal values: 1, 2



Range in g. Default is power-up configuration.

  16 # 16g (1.952 mg/LSB)
   8 #  8g (0.976 mg/LSB)
   4 #  4g (0.488 mg/LSB)
   2 #  2g (0.244 mg/LSB)

Default value: 2

Legal values: 16, 8, 4, 2



Digital filtering cutoff bandwidth. Default is power-up configuration.

   3 # ODR/20 (HP/LP)
   2 # ODR/10 (HP/LP)
   1 # ODR/ 4 (HP/LP)
   0 # ODR/ 2 (up to ODR = 800 Hz, 400 Hz when ODR = 1600 Hz)

Legal values: 3, 2, 1, 0



Specify the sensor power mode. Default is power-up configuration.

  0 # Low Power M1
  1 # Low Power M2
  2 # Low Power M3
  3 # Low Power M4
  4 # High Performance

Legal values: 0, 1, 2, 3, 4



Tap mode. Default is power-up configuration.

  0 # Only Single Tap
  1 # Single and Double Tap

Legal values: 0, 1



Tap X/Y/Z axes threshold. Default is power-up configuration.
(X/Y/Z values range from 0x00 to 0x1F)

Thresholds to start the tap-event detection procedure on the X/Y/Z axes.
Threshold values for each axis are unsigned 5-bit corresponding
to a 2g acceleration full-scale range. A threshold value equal to zero
corresponds to disable the tap detection on that axis.

For example, if you want to set the threshold for X to 12, for Z to 14
and want to disable tap detection on Y, you should specify in Device Tree

    tap-threshold = <12>, <0>, <14>

which is equivalent to X = 12 * 2g/32 = 750mg and Z = 14 * 2g/32 = 875mg.

Default value: [0, 0, 0]



Tap shock value. Default is power-up configuration.
(values range from 0x0 to 0x3)
This register represents the maximum time of an over-threshold signal
detection to be recognized as a tap event. Where 0 equals 4*1/ODR and
1LSB = 8*1/ODR.



Tap latency. Default is power-up configuration.
(values range from 0x0 to 0xF)
When double-tap recognition is enabled, this register expresses the
maximum time between two successive detected taps to determine a
double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR.



Expected quiet time after a tap detection. Default is power-up configuration.
(values range from 0x0 to 0x3)
This register represents the time after the first detected tap in which
there must not be any overthreshold event. Where 0 equals 2*1/ODR
and 1LSB = 4*1/ODR.



Enables the LOW_NOISE flag in the CTRL6 register.
This influences the noise density and the current consumption.
See the datasheet for more information.



Sets the Filtered Data Selection bit in the CTRL6 register.
When enabled, the high-pass filter path is selected.
When disabled, the low-pass filter path is selected.
Note that this influences the OUT_REG / FIFO values,
but not the Wakeup function.



Enables the high-pass filter reference mode in the CTRL7 register.
When the high-pass filter is configured in reference mode,
the output data is calculated as the difference between the input
acceleration and the values captured when reference mode was enabled.
In this way only the difference is applied without any filtering
of the LIS2DW12.
Note that this influences both the OUT_REG / FIFO values,
as well as the Wakeup function.



Selects the pulsed mode for data-ready interrupt when enabled,
and the latched mode when disabled.
Sets the corresponding DRDY_PULSED bit in the CTRL7 register.