This is the documentation for the latest (main) development branch of Zephyr. If you are looking for the documentation of previous releases, use the drop-down list at the bottom of the left panel and select the desired version.


Vendor: Microchip Technology Inc.


These nodes are “spi” bus nodes.

Microchip Polarfire SOC QSPI IP node


Properties not inherited from the base binding file.






Clock frequency the SPI peripheral is being driven at, in Hz.



An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.


  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,

          spi-device@0 {
                  reg = <0>;
          spi-device@1 {
                  reg = <1>;

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.