nordic,nrf-spi

Description

These nodes are “spi” bus nodes.

Nordic nRF family SPI (SPI controller)

Properties

Properties not inherited from the base binding file.

Name

Type

Details

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

This property is required.

max-frequency

int

 
Maximum data rate the SPI peripheral can be driven at, in Hz. This
property must be set at SoC level DTS files.

This property is required.

overrun-character

int

 
Configurable, defaults to 0xff (line high), the most common value used
in SPI transfers.

Default value: 0xff

easydma-maxcnt-bits

int

 
Maximum number of bits available in the EasyDMA MAXCNT register. This
property must be set at SoC level DTS files.

This property is required.

wake-gpios

phandle-array

 
Optional bi-directional line that allows the SPI controller to indicate
to the SPI peripheral (by setting the line high) that a transfer is to
occur, so that
the latter can prepare (and indicate its readiness) for handling that
transfer when it is actually needed, and stay in any desired low-power
state otherwise.
The protocol is as follows:
- initially, the SPI peripheral configures its WAKE line pin as an input
  and the SPI controller keeps the line in the low state
- when a transfer is to be performed, the SPI controller configures its
  WAKE line pin as an input with pull-up; this changes the line state to
  high but allows the SPI peripheral to override that state
- when the SPI peripheral detects the high state of the WAKE line, it
  prepares
  for the transfer and when everything is ready, it drives the WAKE
  line low by configuring its pin as an output
- the generated high-to-low transition on the WAKE line is a signal
  to the SPI controller that it can proceed with the transfer
- the SPI peripheral releases the line by configuring its pin back to be
  an input and the SPI controller again keeps the line in the low state
Please note that the line must be configured and properly handled on
both sides for the mechanism to work correctly.

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.

nordic,clockpin-enable

array

 
List of signals that require CLOCKPIN setting enablement.