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st,stm32h7-spi

Vendor: STMicroelectronics

Description

These nodes are “spi” bus nodes.

STM32H7 SPI controller
This compatible stands for all SPI hardware blocks matching the
version available in STM32H7 SoCs.
This version of STM32 SPI hardware block could be identified by the
presence of a dedicated interrupt enable register (IER).
For instance, but not limited  to: STM32MP1, STM32U5

Properties

Properties not inherited from the base binding file.

Name

Type

Details

midi-clock

int

(Master Inter-Data Idleness) minimum clock inserted
between two consecutive data frames.

mssi-clock

int

(Master SS Idleness) minimum clock inserted between
start and first data transaction.

fifo-enable

boolean

Enable the SPI FIFO usage for performance improvement.

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

This property is required.

clock-frequency

int

Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.