|
#define | MPU_IR_REGION_Msk (0xFFU) |
|
#define | MPU_RBAR_BASE_Pos 6U |
|
#define | MPU_RBAR_BASE_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos) |
|
#define | MPU_RBAR_SH_Pos 4U |
|
#define | MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) |
|
#define | MPU_RBAR_AP_Pos 2U |
|
#define | MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) |
|
#define | MPU_RBAR_XN_Pos 1U |
|
#define | MPU_RBAR_XN_Msk (0x1UL << MPU_RBAR_XN_Pos) |
|
#define | MPU_RLAR_LIMIT_Pos 6U |
|
#define | MPU_RLAR_LIMIT_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos) |
|
#define | MPU_RLAR_AttrIndx_Pos 1U |
|
#define | MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) |
|
#define | MPU_RLAR_EN_Msk (0x1UL) |
|
#define | NOT_EXEC MPU_RBAR_XN_Msk /* PRBAR_EL1 */ |
|
#define | P_RW_U_NA 0x0U |
|
#define | P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
|
#define | P_RW_U_RW 0x1U |
|
#define | P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
|
#define | P_RO_U_NA 0x2U |
|
#define | P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
|
#define | P_RO_U_RO 0x3U |
|
#define | P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) |
|
#define | NON_SHAREABLE 0x0U |
|
#define | NON_SHAREABLE_Msk ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) |
|
#define | OUTER_SHAREABLE 0x2U |
|
#define | OUTER_SHAREABLE_Msk ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) |
|
#define | INNER_SHAREABLE 0x3U |
|
#define | INNER_SHAREABLE_Msk ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) |
|
#define | DEVICE_nGnRnE 0x0U |
|
#define | DEVICE_nGnRE 0x4U |
|
#define | DEVICE_nGRE 0x8U |
|
#define | DEVICE_GRE 0xCU |
|
#define | R_NON_W_NON 0x0U /* Do not allocate Read/Write */ |
|
#define | R_NON_W_ALLOC 0x1U /* Do not allocate Read, Allocate Write */ |
|
#define | R_ALLOC_W_NON 0x2U /* Allocate Read, Do not allocate Write */ |
|
#define | R_ALLOC_W_ALLOC 0x3U /* Allocate Read/Write */ |
|
#define | NORMAL_O_WT_NT 0x80U /* Normal, Outer Write-through non-transient */ |
|
#define | NORMAL_O_WB_NT 0xC0U /* Normal, Outer Write-back non-transient */ |
|
#define | NORMAL_O_NON_C 0x40U /* Normal, Outer Non-Cacheable */ |
|
#define | NORMAL_I_WT_NT 0x08U /* Normal, Inner Write-through non-transient */ |
|
#define | NORMAL_I_WB_NT 0x0CU /* Normal, Inner Write-back non-transient */ |
|
#define | NORMAL_I_NON_C 0x04U /* Normal, Inner Non-Cacheable */ |
|
#define | MPU_MAIR_INDEX_DEVICE 0U |
|
#define | MPU_MAIR_ATTR_DEVICE (DEVICE_nGnRnE) |
|
#define | MPU_MAIR_INDEX_FLASH 1U |
|
#define | MPU_MAIR_ATTR_FLASH |
|
#define | MPU_MAIR_INDEX_SRAM 2U |
|
#define | MPU_MAIR_ATTR_SRAM |
|
#define | MPU_MAIR_INDEX_SRAM_NOCACHE 3U |
|
#define | MPU_MAIR_ATTR_SRAM_NOCACHE |
|
#define | MPU_MAIR_ATTRS |
|
#define | REGION_IO_ATTR |
|
#define | REGION_RAM_ATTR |
|
#define | REGION_RAM_NOCACHE_ATTR |
|
#define | REGION_RAM_TEXT_ATTR |
|
#define | REGION_RAM_RO_ATTR |
|
#define | REGION_FLASH_ATTR |
|
#define | MPU_REGION_ENTRY(_name, _base, _limit, _attr) |
|
#define | K_MEM_PARTITION_P_RW_U_RW |
|
#define | K_MEM_PARTITION_P_RW_U_NA |
|
#define | K_MEM_PARTITION_P_RO_U_RO |
|
#define | K_MEM_PARTITION_P_RO_U_NA |
|
#define | ARM64_MPU_MAX_DYNAMIC_REGIONS |
|