ads1220.h

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/*
 * Copyright (c) 2025 Baumer Group
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1220_H_
#define ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1220_H_

 
#ifdef __cplusplus
extern "C" {
#endif


#define ADS1220_RESOLUTION 24u
#define ADS1220_CHANNELS   4u
#define ADS1220_CHANNEL_ID 0x00u

#define ADS1220_REG0_MUX_MSK         0xF0u
#define ADS1220_REG0_MUX_AIN0_AIN1   (0x0u << 0x04)
#define ADS1220_REG0_MUX_AIN0_AIN2   (0x1u << 0x04)
#define ADS1220_REG0_MUX_AIN0_AIN3   (0x2u << 0x04)
#define ADS1220_REG0_MUX_AIN1_AIN2   (0x3u << 0x04)
#define ADS1220_REG0_MUX_AIN1_AIN3   (0x4u << 0x04)
#define ADS1220_REG0_MUX_AIN2_AIN3   (0x5u << 0x04)
#define ADS1220_REG0_MUX_AIN1_AIN0   (0x6u << 0x04)
#define ADS1220_REG0_MUX_AIN3_AIN2   (0x7u << 0x04)
#define ADS1220_REG0_MUX_AIN0_AVSS   (0x8u << 0x04)
#define ADS1220_REG0_MUX_AIN1_AVSS   (0x9u << 0x04)
#define ADS1220_REG0_MUX_AIN2_AVSS   (0xAu << 0x04)
#define ADS1220_REG0_MUX_AIN3_AVSS   (0xBu << 0x04)
#define ADS1220_REG0_MUX_V_REF       (0xCu << 0x04)
#define ADS1220_REG0_MUX_AVDD_AVSS_1 (0xDu << 0x04)
#define ADS1220_REG0_MUX_AVDD_AVSS_2 (0xEu << 0x04)
#define ADS1220_REG0_MUX_RESERVED    (0xFu << 0x04)

#define ADS1220_REG0_GAIN_MSK 0x0Eu
#define ADS1220_REG0_GAIN_1   (0x0u << 0x01)
#define ADS1220_REG0_GAIN_2   (0x1u << 0x01)
#define ADS1220_REG0_GAIN_4   (0x2u << 0x01)
#define ADS1220_REG0_GAIN_8   (0x3u << 0x01)
#define ADS1220_REG0_GAIN_16  (0x4u << 0x01)
#define ADS1220_REG0_GAIN_32  (0x5u << 0x01)
#define ADS1220_REG0_GAIN_64  (0x6u << 0x01)
#define ADS1220_REG0_GAIN_128 (0x7u << 0x01)

#define ADS1220_REG0_PGA_BYPASS BIT(0)

#define ADS1220_REG1_DR_MSK 0xE0u
#define ADS1220_REG1_DR_POS 0x5u

#define ADS1220_REG1_MODE_MSK        0x18u
#define ADS1220_REG1_MODE_POS        0x3u
#define ADS1220_REG1_MODE_NORMAL     (0x0u << 0x03)
#define ADS1220_REG1_MODE_DUTY_CYCLE (0x1u << 0x03)
#define ADS1220_REG1_MODE_TURBO      (0x2u << 0x03)

#define ADS1220_REG1_CM  BIT(2)
#define ADS1220_REG1_TS  BIT(1)
#define ADS1220_REG1_BCS BIT(0)

#define ADS1220_REG2_VREF_MSK    0xC0u
#define ADS1220_REG2_VREF_INT    (0x0u << 0x06)
#define ADS1220_REG2_VREF_EXT_0  (0x1u << 0x06)
#define ADS1220_REG2_VREF_EXT_1  (0x2u << 0x06)
#define ADS1220_REG2_VREF_SUPPLY (0x3u << 0x06)

#define ADS1220_REG2_50_60HZ_MSK  0x30u
#define ADS1220_REG2_50_60HZ_NONE (0x0u << 0x04)
#define ADS1220_REG2_50_60HZ_50HZ (0x1u << 0x04)
#define ADS1220_REG2_50_60HZ_60HZ (0x2u << 0x04)
#define ADS1220_REG2_50_60HZ_BOTH (0x3u << 0x04)

#define ADS1220_REG2_PSW BIT(3)

#define ADS1220_REG2_IDAC_MSK    0x07u
#define ADS1220_REG2_IDAC_OFF    (0x0u)
#define ADS1220_REG2_IDAC_10UA   (0x1u)
#define ADS1220_REG2_IDAC_50UA   (0x2u)
#define ADS1220_REG2_IDAC_100UA  (0x3u)
#define ADS1220_REG2_IDAC_250UA  (0x4u)
#define ADS1220_REG2_IDAC_500UA  (0x5u)
#define ADS1220_REG2_IDAC_1000UA (0x6u)
#define ADS1220_REG2_IDAC_1500UA (0x7u)

#define ADS1220_REG3_I1MUX_MSK        0xE0u
#define ADS1220_REG3_I1MUX_POS        0x5u
#define ADS1220_REG3_I1MUX_DISABLED   (0x0u << 0x05)
#define ADS1220_REG3_I1MUX_AIN0_REFP1 (0x1u << 0x05)
#define ADS1220_REG3_I1MUX_AIN1       (0x2u << 0x05)
#define ADS1220_REG3_I1MUX_AIN2       (0x3u << 0x05)
#define ADS1220_REG3_I1MUX_AIN3_REFN1 (0x4u << 0x05)
#define ADS1220_REG3_I1MUX_REFP       (0x5u << 0x05)
#define ADS1220_REG3_I1MUX_REFN       (0x6u << 0x05)

#define ADS1220_REG3_I2MUX_MSK        0x1Cu
#define ADS1220_REG3_I2MUX_POS        0x2u
#define ADS1220_REG3_I2MUX_DISABLED   (0x0u << 0x02)
#define ADS1220_REG3_I2MUX_AIN0_REFP1 (0x1u << 0x02)
#define ADS1220_REG3_I2MUX_AIN1       (0x2u << 0x02)
#define ADS1220_REG3_I2MUX_AIN2       (0x3u << 0x02)
#define ADS1220_REG3_I2MUX_AIN3_REFN1 (0x4u << 0x02)
#define ADS1220_REG3_I2MUX_REFP       (0x5u << 0x02)
#define ADS1220_REG3_I2MUX_REFN       (0x6u << 0x02)

#define ADS1220_REG3_DRDYM    BIT(1)
#define ADS1220_REG3_RESERVED BIT(0)

 
#ifdef __cplusplus
}
#endif
 
#endif /* INCLUDE_ESF_DRIVERS_ADC_ADS1220_H */