Zephyr API Documentation 4.3.99
A Scalable Open Source RTOS
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alif-ensemble-clocks.h
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1/*
2 * Copyright (c) 2025 Alif Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_
9
17
18#include "alif-clocks-common.h"
19
24
26#define ALIF_UART_CTRL_REG 0x08U
27
29
34
36#define ALIF_UART0_SYST_PCLK \
37 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)
38
39#define ALIF_UART1_SYST_PCLK \
40 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)
41
42#define ALIF_UART2_SYST_PCLK \
43 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)
44
45#define ALIF_UART3_SYST_PCLK \
46 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)
47
48#define ALIF_UART4_SYST_PCLK \
49 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)
50
51#define ALIF_UART5_SYST_PCLK \
52 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)
53
54#define ALIF_UART6_SYST_PCLK \
55 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 6U, 1U, 1U, 1U, 14U, ALIF_PARENT_CLK_SYST_PCLK)
56
57#define ALIF_UART7_SYST_PCLK \
58 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 7U, 1U, 1U, 1U, 15U, ALIF_PARENT_CLK_SYST_PCLK)
59
61
62#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_ */
alif-clocks-common.h
Common clock definitions for Alif Semiconductor SoC families.