alif-ensemble-clocks.h File Reference

Clock IDs for Alif Ensemble SoC family. More...

#include "alif-clocks-common.h"

Go to the source code of this file.

Macros
Register offsets
#define	ALIF_UART_CTRL_REG   0x08U
	UART control register offset in CLKCTL_PER_SLV.
UART peripheral clocks
#define	ALIF_UART0_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)
	UART0 clock sourced from system PCLK.
#define	ALIF_UART1_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)
	UART1 clock sourced from system PCLK.
#define	ALIF_UART2_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)
	UART2 clock sourced from system PCLK.
#define	ALIF_UART3_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)
	UART3 clock sourced from system PCLK.
#define	ALIF_UART4_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)
	UART4 clock sourced from system PCLK.
#define	ALIF_UART5_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)
	UART5 clock sourced from system PCLK.
#define	ALIF_UART6_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 6U, 1U, 1U, 1U, 14U, ALIF_PARENT_CLK_SYST_PCLK)
	UART6 clock sourced from system PCLK.
#define	ALIF_UART7_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 7U, 1U, 1U, 1U, 15U, ALIF_PARENT_CLK_SYST_PCLK)
	UART7 clock sourced from system PCLK.

Detailed Description

Clock IDs for Alif Ensemble SoC family.

Defines peripheral clock identifiers for the Alif Ensemble family. Each clock ID is encoded using ALIF_CLK_CFG() macro from alif-clocks-common.h.

Macro Definition Documentation

ALIF_UART0_SYST_PCLK

#define ALIF_UART0_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)

UART0 clock sourced from system PCLK.

ALIF_UART1_SYST_PCLK

#define ALIF_UART1_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)

UART1 clock sourced from system PCLK.

ALIF_UART2_SYST_PCLK

#define ALIF_UART2_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)

UART2 clock sourced from system PCLK.

ALIF_UART3_SYST_PCLK

#define ALIF_UART3_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)

UART3 clock sourced from system PCLK.

ALIF_UART4_SYST_PCLK

#define ALIF_UART4_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)

UART4 clock sourced from system PCLK.

ALIF_UART5_SYST_PCLK

#define ALIF_UART5_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)

UART5 clock sourced from system PCLK.

ALIF_UART6_SYST_PCLK

#define ALIF_UART6_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 6U, 1U, 1U, 1U, 14U, ALIF_PARENT_CLK_SYST_PCLK)

UART6 clock sourced from system PCLK.

ALIF_UART7_SYST_PCLK

#define ALIF_UART7_SYST_PCLK    ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 7U, 1U, 1U, 1U, 15U, ALIF_PARENT_CLK_SYST_PCLK)

UART7 clock sourced from system PCLK.

ALIF_UART_CTRL_REG

#define ALIF_UART_CTRL_REG   0x08U

UART control register offset in CLKCTL_PER_SLV.