Zephyr API Documentation 4.3.99
A Scalable Open Source RTOS
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amebad_clock.h
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1/*
2 * Copyright (c) 2024 Realtek Semiconductor Corp.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AMEBAD_CLOCK_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AMEBAD_CLOCK_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif
13
18
23
25#define AMEBA_ATIM_CLK 0
26
28#define AMEBA_RTC_CLK 1
29
31
36
38#define AMEBA_PWM0_CLK 2
39
41#define AMEBA_UART0_CLK 3
42
44#define AMEBA_LOGUART_CLK 4
45
47#define AMEBA_UART3_CLK 5
48
50#define AMEBA_ADC_CLK 6
51
53#define AMEBA_GPIO_CLK 7
54
56#define AMEBA_LTIM0_CLK 8
57
59#define AMEBA_LTIM1_CLK 9
60
62#define AMEBA_LTIM2_CLK 10
63
65#define AMEBA_LTIM3_CLK 11
66
68
73
75#define AMEBA_PERI_HCLK 12
76
78#define AMEBA_GDMA0_CLK 13
79
81#define AMEBA_SPI0_CLK 14
82
84#define AMEBA_SPI1_CLK 15
85
87#define AMEBA_FLASH_CLK 16
88
90#define AMEBA_PSRAM_CLK 17
91
93#define AMEBA_I2C0_CLK 18
94
96#define AMEBA_PRNG_CLK 19
97
101#define AMEBA_CLK_MAX 20 /* clk idx max */
102
104
109
118#define AMEBA_NUMERICAL_PERIPH(name, n) \
119 [AMEBA_##name##n##_CLK] = { \
120 .parent = AMEBA_RCC_NO_PARENT, \
121 .cke = APBPeriph_##name##n##_CLOCK, \
122 .fen = APBPeriph_##name##n, \
123 },
124
133#define AMEBA_SINGLE_PERIPH(name) \
134 [AMEBA_##name##_CLK] = { \
135 .parent = AMEBA_RCC_NO_PARENT, \
136 .cke = APBPeriph_##name##_CLOCK, \
137 .fen = APBPeriph_##name, \
138 },
139
148#define AMEBA_REMAP_PERIPH(clk_index, remap_name) \
149 [clk_index] = { \
150 .parent = AMEBA_RCC_NO_PARENT, \
151 .cke = APBPeriph_##remap_name##_CLOCK, \
152 .fen = APBPeriph_##remap_name, \
153 },
154
158#define AMEBA_LTIM_PERIPHS \
159 AMEBA_REMAP_PERIPH(AMEBA_LTIM0_CLK, GTIMER) \
160 AMEBA_REMAP_PERIPH(AMEBA_LTIM1_CLK, GTIMER) \
161 AMEBA_REMAP_PERIPH(AMEBA_LTIM2_CLK, GTIMER) \
162 AMEBA_REMAP_PERIPH(AMEBA_LTIM3_CLK, GTIMER)
163
167#define AMEBA_PWM_PERIPHS AMEBA_REMAP_PERIPH(AMEBA_PWM0_CLK, GTIMER)
168
172#define AMEBA_SPI_PERIPHS \
173 AMEBA_NUMERICAL_PERIPH(SPI, 0) /* AMEBA_SPI0_CLK */ \
174 AMEBA_NUMERICAL_PERIPH(SPI, 1) /* AMEBA_SPI1_CLK */
175
179#define AMEBA_I2C_PERIPHS AMEBA_NUMERICAL_PERIPH(I2C, 0) /* AMEBA_I2C0_CLK */
180
184#define AMEBA_UART_PERIPHS \
185 AMEBA_NUMERICAL_PERIPH(UART, 0) /* AMEBA_UART0_CLK */ \
186 AMEBA_NUMERICAL_PERIPH(UART, 3) /* AMEBA_UART3_CLK */
187
191#define AMEBA_GDMA0_PERIPHS AMEBA_SINGLE_PERIPH(GDMA0) /* AMEBA_GDMA0_CLK */
192
196#define AMEBA_PSRAM_PERIPHS AMEBA_SINGLE_PERIPH(PSRAM) /* AMEBA_PSRAM_CLK */
197
201#define AMEBA_RTC_PERIPHS AMEBA_SINGLE_PERIPH(RTC) /* AMEBA_RTC_CLK */
202
208#define AMEBA_LOGUART_PERIPHS AMEBA_REMAP_PERIPH(AMEBA_LOGUART_CLK, NULL)
209
213#define AMEBA_FLASH_PERIPHS AMEBA_REMAP_PERIPH(AMEBA_FLASH_CLK, NULL)
214
218#define AMEBA_GPIO_PERIPHS AMEBA_REMAP_PERIPH(AMEBA_GPIO_CLK, NULL)
219
223#define AMEBA_ADC_PERIPHS AMEBA_REMAP_PERIPH(AMEBA_ADC_CLK, NULL)
224
228#define AMEBA_PRNG_PERIPHS AMEBA_REMAP_PERIPH(AMEBA_PRNG_CLK, NULL)
229
235#define APBPeriph_NULL_CLOCK APBPeriph_CLOCK_NULL
236
243#define AMEBA_CORE_PERIPHS \
244 AMEBA_RTC_PERIPHS \
245 AMEBA_PWM_PERIPHS \
246 AMEBA_UART_PERIPHS \
247 AMEBA_LOGUART_PERIPHS \
248 AMEBA_ADC_PERIPHS \
249 AMEBA_GPIO_PERIPHS \
250 AMEBA_LTIM_PERIPHS \
251 AMEBA_GDMA0_PERIPHS \
252 AMEBA_SPI_PERIPHS \
253 AMEBA_FLASH_PERIPHS \
254 AMEBA_I2C_PERIPHS \
255 AMEBA_PRNG_PERIPHS
256
258
259#ifdef __cplusplus
260}
261#endif
262
263#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AMEBAD_CLOCK_H_ */