amebad_clock.h File Reference

Realtek Amebad clock Devicetree bindings. More...

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Macros
AON domain clocks
#define	AMEBA_ATIM_CLK   0
	ATIM clock in AON domain.
#define	AMEBA_RTC_CLK   1
	RTC clock in AON domain.
SYSON domain clocks
#define	AMEBA_PWM0_CLK   2
	PWM0 clock in SYSON domain.
#define	AMEBA_UART0_CLK   3
	UART0 clock in SYSON domain.
#define	AMEBA_LOGUART_CLK   4
	LOGUART clock in SYSON domain.
#define	AMEBA_UART3_CLK   5
	UART3 clock in SYSON domain.
#define	AMEBA_ADC_CLK   6
	ADC clock in SYSON domain.
#define	AMEBA_GPIO_CLK   7
	GPIO clock in SYSON domain.
#define	AMEBA_LTIM0_CLK   8
	LTIM0 clock in SYSON domain.
#define	AMEBA_LTIM1_CLK   9
	LTIM1 clock in SYSON domain.
#define	AMEBA_LTIM2_CLK   10
	LTIM2 clock in SYSON domain.
#define	AMEBA_LTIM3_CLK   11
	LTIM3 clock in SYSON domain.
SoC domain clocks
#define	AMEBA_PERI_HCLK   12
	Peripheral HCLK in SoC domain.
#define	AMEBA_GDMA0_CLK   13
	GDMA0 clock in SoC domain.
#define	AMEBA_SPI0_CLK   14
	SPI0 clock in SoC domain.
#define	AMEBA_SPI1_CLK   15
	SPI1 clock in SoC domain.
#define	AMEBA_FLASH_CLK   16
	Flash clock in SoC domain.
#define	AMEBA_PSRAM_CLK   17
	PSRAM clock in SoC domain.
#define	AMEBA_I2C0_CLK   18
	I2C0 clock in SoC domain.
#define	AMEBA_PRNG_CLK   19
	PRNG clock in SoC domain.
#define	AMEBA_CLK_MAX   20 /* clk idx max */
	Maximum clock index (one past the last valid index).
Peripheral clock helper macros
#define	AMEBA_NUMERICAL_PERIPH(name, n)
	Define a clock entry for a peripheral with numerical suffix.
#define	AMEBA_SINGLE_PERIPH(name)
	Define a clock entry for a single-instance peripheral.
#define	AMEBA_REMAP_PERIPH(clk_index, remap_name)
	Define a clock entry with a remapped peripheral name.
#define	AMEBA_LTIM_PERIPHS
	LTIM clock mappings to GTIMER peripheral.
#define	AMEBA_PWM_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_PWM0_CLK, GTIMER)
	PWM clock mapping to GTIMER peripheral.
#define	AMEBA_SPI_PERIPHS
	SPI clock peripheral mappings.
#define	AMEBA_I2C_PERIPHS   AMEBA_NUMERICAL_PERIPH(I2C, 0) /* AMEBA_I2C0_CLK */
	I2C clock peripheral mappings.
#define	AMEBA_UART_PERIPHS
	UART clock peripheral mappings.
#define	AMEBA_GDMA0_PERIPHS   AMEBA_SINGLE_PERIPH(GDMA0) /* AMEBA_GDMA0_CLK */
	GDMA0 clock peripheral mapping.
#define	AMEBA_PSRAM_PERIPHS   AMEBA_SINGLE_PERIPH(PSRAM) /* AMEBA_PSRAM_CLK */
	PSRAM clock peripheral mapping.
#define	AMEBA_RTC_PERIPHS   AMEBA_SINGLE_PERIPH(RTC) /* AMEBA_RTC_CLK */
	RTC clock peripheral mapping.
#define	AMEBA_LOGUART_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_LOGUART_CLK, NULL)
	LOGUART clock peripheral mapping.
#define	AMEBA_FLASH_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_FLASH_CLK, NULL)
	Flash clock peripheral mapping.
#define	AMEBA_GPIO_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_GPIO_CLK, NULL)
	GPIO clock peripheral mapping.
#define	AMEBA_ADC_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_ADC_CLK, NULL)
	ADC clock peripheral mapping.
#define	AMEBA_PRNG_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_PRNG_CLK, NULL)
	PRNG clock peripheral mapping.
#define	APBPeriph_NULL_CLOCK   APBPeriph_CLOCK_NULL
	Null APB peripheral clock definition.
#define	AMEBA_CORE_PERIPHS
	Aggregated core peripheral clock mappings.

Detailed Description

Realtek Amebad clock Devicetree bindings.

Macro Definition Documentation

AMEBA_ADC_CLK

#define AMEBA_ADC_CLK   6

ADC clock in SYSON domain.

AMEBA_ADC_PERIPHS

#define AMEBA_ADC_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_ADC_CLK, NULL)

ADC clock peripheral mapping.

AMEBA_ATIM_CLK

#define AMEBA_ATIM_CLK   0

ATIM clock in AON domain.

AMEBA_CLK_MAX

#define AMEBA_CLK_MAX   20 /* clk idx max */

Maximum clock index (one past the last valid index).

AMEBA_CORE_PERIPHS

#define AMEBA_CORE_PERIPHS

Value:

        AMEBA_RTC_PERIPHS                                                                  \
        AMEBA_PWM_PERIPHS                                                                  \
        AMEBA_UART_PERIPHS                                                                 \
        AMEBA_LOGUART_PERIPHS                                                              \
        AMEBA_ADC_PERIPHS                                                                  \
        AMEBA_GPIO_PERIPHS                                                                 \
        AMEBA_LTIM_PERIPHS                                                                 \
        AMEBA_GDMA0_PERIPHS                                                                \
        AMEBA_SPI_PERIPHS                                                                  \
        AMEBA_FLASH_PERIPHS                                                                \
        AMEBA_I2C_PERIPHS                                                                  \
        AMEBA_PRNG_PERIPHS

Aggregated core peripheral clock mappings.

This macro expands to mappings of all core peripherals used by the clock control implementation.

AMEBA_FLASH_CLK

#define AMEBA_FLASH_CLK   16

Flash clock in SoC domain.

AMEBA_FLASH_PERIPHS

#define AMEBA_FLASH_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_FLASH_CLK, NULL)

Flash clock peripheral mapping.

AMEBA_GDMA0_CLK

#define AMEBA_GDMA0_CLK   13

GDMA0 clock in SoC domain.

AMEBA_GDMA0_PERIPHS

#define AMEBA_GDMA0_PERIPHS   AMEBA_SINGLE_PERIPH(GDMA0) /* AMEBA_GDMA0_CLK */

GDMA0 clock peripheral mapping.

AMEBA_GPIO_CLK

#define AMEBA_GPIO_CLK   7

GPIO clock in SYSON domain.

AMEBA_GPIO_PERIPHS

#define AMEBA_GPIO_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_GPIO_CLK, NULL)

GPIO clock peripheral mapping.

AMEBA_I2C0_CLK

#define AMEBA_I2C0_CLK   18

I2C0 clock in SoC domain.

AMEBA_I2C_PERIPHS

#define AMEBA_I2C_PERIPHS   AMEBA_NUMERICAL_PERIPH(I2C, 0) /* AMEBA_I2C0_CLK */

I2C clock peripheral mappings.

AMEBA_LOGUART_CLK

#define AMEBA_LOGUART_CLK   4

LOGUART clock in SYSON domain.

AMEBA_LOGUART_PERIPHS

#define AMEBA_LOGUART_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_LOGUART_CLK, NULL)

LOGUART clock peripheral mapping.

TODO: Enabled in KM0.

AMEBA_LTIM0_CLK

#define AMEBA_LTIM0_CLK   8

LTIM0 clock in SYSON domain.

AMEBA_LTIM1_CLK

#define AMEBA_LTIM1_CLK   9

LTIM1 clock in SYSON domain.

AMEBA_LTIM2_CLK

#define AMEBA_LTIM2_CLK   10

LTIM2 clock in SYSON domain.

AMEBA_LTIM3_CLK

#define AMEBA_LTIM3_CLK   11

LTIM3 clock in SYSON domain.

AMEBA_LTIM_PERIPHS

#define AMEBA_LTIM_PERIPHS

Value:

        AMEBA_REMAP_PERIPH(AMEBA_LTIM0_CLK, GTIMER)                                        \
        AMEBA_REMAP_PERIPH(AMEBA_LTIM1_CLK, GTIMER)                                        \
        AMEBA_REMAP_PERIPH(AMEBA_LTIM2_CLK, GTIMER)                                        \
        AMEBA_REMAP_PERIPH(AMEBA_LTIM3_CLK, GTIMER)

LTIM clock mappings to GTIMER peripheral.

AMEBA_NUMERICAL_PERIPH

#define AMEBA_NUMERICAL_PERIPH	(		name,
			n )

Value:

        [AMEBA_##name##n##_CLK] = {                                                        \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##name##n##_CLOCK,                                        \
                .fen = APBPeriph_##name##n,                                                \
        },

Define a clock entry for a peripheral with numerical suffix.

Used for peripherals with an index, for example SPI0, SPI1, UART0.

Parameters

name	Peripheral base name
n	Peripheral index

AMEBA_PERI_HCLK

#define AMEBA_PERI_HCLK   12

Peripheral HCLK in SoC domain.

AMEBA_PRNG_CLK

#define AMEBA_PRNG_CLK   19

PRNG clock in SoC domain.

AMEBA_PRNG_PERIPHS

#define AMEBA_PRNG_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_PRNG_CLK, NULL)

PRNG clock peripheral mapping.

AMEBA_PSRAM_CLK

#define AMEBA_PSRAM_CLK   17

PSRAM clock in SoC domain.

AMEBA_PSRAM_PERIPHS

#define AMEBA_PSRAM_PERIPHS   AMEBA_SINGLE_PERIPH(PSRAM) /* AMEBA_PSRAM_CLK */

PSRAM clock peripheral mapping.

AMEBA_PWM0_CLK

#define AMEBA_PWM0_CLK   2

PWM0 clock in SYSON domain.

AMEBA_PWM_PERIPHS

#define AMEBA_PWM_PERIPHS   AMEBA_REMAP_PERIPH(AMEBA_PWM0_CLK, GTIMER)

PWM clock mapping to GTIMER peripheral.

AMEBA_REMAP_PERIPH

#define AMEBA_REMAP_PERIPH	(		clk_index,
			remap_name )

Value:

        [clk_index] = {                                                                    \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##remap_name##_CLOCK,                                     \
                .fen = APBPeriph_##remap_name,                                             \
        },

Define a clock entry with a remapped peripheral name.

Used when a clock index is mapped to another peripheral name.

Parameters

clk_index	Clock index
remap_name	Target peripheral name

AMEBA_RTC_CLK

#define AMEBA_RTC_CLK   1

RTC clock in AON domain.

AMEBA_RTC_PERIPHS

#define AMEBA_RTC_PERIPHS   AMEBA_SINGLE_PERIPH(RTC) /* AMEBA_RTC_CLK */

RTC clock peripheral mapping.

AMEBA_SINGLE_PERIPH

#define AMEBA_SINGLE_PERIPH

(

name

)

Value:

        [AMEBA_##name##_CLK] = {                                                           \
                .parent = AMEBA_RCC_NO_PARENT,                                             \
                .cke = APBPeriph_##name##_CLOCK,                                           \
                .fen = APBPeriph_##name,                                                   \
        },

Define a clock entry for a single-instance peripheral.

Used for peripherals that have only one instance, for example GDMA0, PSRAM, RTC.

Parameters

name	Peripheral name

AMEBA_SPI0_CLK

#define AMEBA_SPI0_CLK   14

SPI0 clock in SoC domain.

AMEBA_SPI1_CLK

#define AMEBA_SPI1_CLK   15

SPI1 clock in SoC domain.

AMEBA_SPI_PERIPHS

#define AMEBA_SPI_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(SPI, 0) /* AMEBA_SPI0_CLK */                                \
        AMEBA_NUMERICAL_PERIPH(SPI, 1) /* AMEBA_SPI1_CLK */

SPI clock peripheral mappings.

AMEBA_UART0_CLK

#define AMEBA_UART0_CLK   3

UART0 clock in SYSON domain.

AMEBA_UART3_CLK

#define AMEBA_UART3_CLK   5

UART3 clock in SYSON domain.

AMEBA_UART_PERIPHS

#define AMEBA_UART_PERIPHS

Value:

        AMEBA_NUMERICAL_PERIPH(UART, 0) /* AMEBA_UART0_CLK */                              \
        AMEBA_NUMERICAL_PERIPH(UART, 3) /* AMEBA_UART3_CLK */

UART clock peripheral mappings.

APBPeriph_NULL_CLOCK

#define APBPeriph_NULL_CLOCK   APBPeriph_CLOCK_NULL

Null APB peripheral clock definition.

Used as a placeholder for an invalid or unused APB clock.