cpu.h File Reference

#include <zephyr/sys/util_macro.h>
#include <stdbool.h>

Go to the source code of this file.

Macros
#define	DAIFSET_FIQ_BIT   BIT(0)
#define	DAIFSET_IRQ_BIT   BIT(1)
#define	DAIFSET_ABT_BIT   BIT(2)
#define	DAIFSET_DBG_BIT   BIT(3)
#define	DAIFCLR_FIQ_BIT   BIT(0)
#define	DAIFCLR_IRQ_BIT   BIT(1)
#define	DAIFCLR_ABT_BIT   BIT(2)
#define	DAIFCLR_DBG_BIT   BIT(3)
#define	DAIF_FIQ_BIT   BIT(6)
#define	DAIF_IRQ_BIT   BIT(7)
#define	DAIF_ABT_BIT   BIT(8)
#define	DAIF_DBG_BIT   BIT(9)
#define	SPSR_DAIF_SHIFT   (6)
#define	SPSR_DAIF_MASK   (0xf << SPSR_DAIF_SHIFT)
#define	SPSR_MODE_EL0T   (0x0)
#define	SPSR_MODE_EL1T   (0x4)
#define	SPSR_MODE_EL1H   (0x5)
#define	SPSR_MODE_EL2T   (0x8)
#define	SPSR_MODE_EL2H   (0x9)
#define	SPSR_MODE_MASK   (0xf)
#define	SCTLR_EL3_RES1
#define	SCTLR_EL2_RES1
#define	SCTLR_EL1_RES1
#define	SCTLR_M_BIT   BIT(0)
#define	SCTLR_A_BIT   BIT(1)
#define	SCTLR_C_BIT   BIT(2)
#define	SCTLR_SA_BIT   BIT(3)
#define	SCTLR_I_BIT   BIT(12)
#define	SCTLR_BR_BIT   BIT(17)
#define	CPACR_EL1_FPEN   GENMASK(21, 20)
#define	CPACR_EL1_ZEN   GENMASK(17, 16)
#define	SCR_NS_BIT   BIT(0)
#define	SCR_IRQ_BIT   BIT(1)
#define	SCR_FIQ_BIT   BIT(2)
#define	SCR_EA_BIT   BIT(3)
#define	SCR_SMD_BIT   BIT(7)
#define	SCR_HCE_BIT   BIT(8)
#define	SCR_RW_BIT   BIT(10)
#define	SCR_ST_BIT   BIT(11)
#define	SCR_EEL2_BIT   BIT(18)
#define	SCR_RES1   (BIT(4) | BIT(5))
#define	MPIDR_AFFLVL_MASK   (0xffULL)
#define	MPIDR_AFF0_SHIFT   (0)
#define	MPIDR_AFF1_SHIFT   (8)
#define	MPIDR_AFF2_SHIFT   (16)
#define	MPIDR_AFF3_SHIFT   (32)
#define	MPIDR_AFF_MASK   (GENMASK(23, 0) | GENMASK(39, 32))
#define	MPIDR_AFFLVL(mpidr, aff_level)
#define	GET_MPIDR()
#define	MPIDR_TO_CORE(mpidr)
#define	MODE_EL_SHIFT   (0x2)
#define	MODE_EL_MASK   (0x3)
#define	MODE_EL3   (0x3)
#define	MODE_EL2   (0x2)
#define	MODE_EL1   (0x1)
#define	MODE_EL0   (0x0)
#define	GET_EL(_mode)
#define	ESR_EC_SHIFT   (26)
#define	ESR_EC_MASK   BIT_MASK(6)
#define	ESR_ISS_SHIFT   (0)
#define	ESR_ISS_MASK   BIT_MASK(25)
#define	ESR_IL_SHIFT   (25)
#define	ESR_IL_MASK   BIT_MASK(1)
#define	GET_ESR_EC(esr)
#define	GET_ESR_IL(esr)
#define	GET_ESR_ISS(esr)
#define	CNTV_CTL_ENABLE_BIT   BIT(0)
#define	CNTV_CTL_IMASK_BIT   BIT(1)
#define	ID_AA64PFR0_EL0_SHIFT   (0)
#define	ID_AA64PFR0_EL1_SHIFT   (4)
#define	ID_AA64PFR0_EL2_SHIFT   (8)
#define	ID_AA64PFR0_EL3_SHIFT   (12)
#define	ID_AA64PFR0_ELX_MASK   (0xf)
#define	ID_AA64PFR0_FP_SHIFT   (16)
#define	ID_AA64PFR0_FP_MASK   (0xf)
#define	ID_AA64PFR0_ADVSIMD_SHIFT   (20)
#define	ID_AA64PFR0_ADVSIMD_MASK   (0xf)
#define	ID_AA64PFR0_SVE_SHIFT   (32)
#define	ID_AA64PFR0_SVE_MASK   (0xf)
#define	ID_AA64PFR0_SEL2_SHIFT   (36)
#define	ID_AA64PFR0_SEL2_MASK   (0xf)
#define	ACTLR_EL3_CPUACTLR_BIT   BIT(0)
#define	ACTLR_EL3_CPUECTLR_BIT   BIT(1)
#define	ACTLR_EL3_L2CTLR_BIT   BIT(4)
#define	ACTLR_EL3_L2ECTLR_BIT   BIT(5)
#define	ACTLR_EL3_L2ACTLR_BIT   BIT(6)
#define	CPTR_EZ_BIT   BIT(8)
#define	CPTR_TFP_BIT   BIT(10)
#define	CPTR_TTA_BIT   BIT(20)
#define	CPTR_TCPAC_BIT   BIT(31)
#define	CPTR_EL2_TZ_BIT   BIT(8)
#define	CPTR_EL2_ZEN_SHIFT   16
#define	CPTR_EL2_ZEN_MASK   (0x3 << CPTR_EL2_ZEN_SHIFT)
#define	CPTR_EL2_ZEN_EL1_EN   BIT(16)
#define	CPTR_EL2_ZEN_EL0_EN   BIT(17)
#define	CPTR_EL2_RES1   BIT(13) | BIT(12) | BIT(9) | (0xff)
#define	ZCR_EL1   S3_0_C1_C2_0
#define	ZCR_EL2   S3_4_C1_C2_0
#define	ZCR_EL3   S3_6_C1_C2_0
#define	HCR_FMO_BIT   BIT(3)
#define	HCR_IMO_BIT   BIT(4)
#define	HCR_AMO_BIT   BIT(5)
#define	HCR_TGE_BIT   BIT(27)
#define	HCR_RW_BIT   BIT(31)
#define	ICC_IGRPEN1_EL1   S3_0_C12_C12_7
#define	ICC_SGI1R   S3_0_C12_C11_5
#define	ICC_SRE_EL1   S3_0_C12_C12_5
#define	ICC_SRE_EL2   S3_4_C12_C9_5
#define	ICC_SRE_EL3   S3_6_C12_C12_5
#define	ICC_CTLR_EL1   S3_0_C12_C12_4
#define	ICC_CTLR_EL3   S3_6_C12_C12_4
#define	ICC_PMR_EL1   S3_0_C4_C6_0
#define	ICC_RPR_EL1   S3_0_C12_C11_3
#define	ICC_IGRPEN1_EL3   S3_6_C12_C12_7
#define	ICC_IGRPEN0_EL1   S3_0_C12_C12_6
#define	ICC_HPPIR0_EL1   S3_0_C12_C8_2
#define	ICC_HPPIR1_EL1   S3_0_C12_C12_2
#define	ICC_IAR0_EL1   S3_0_C12_C8_0
#define	ICC_IAR1_EL1   S3_0_C12_C12_0
#define	ICC_EOIR0_EL1   S3_0_C12_C8_1
#define	ICC_EOIR1_EL1   S3_0_C12_C12_1
#define	ICC_SGI0R_EL1   S3_0_C12_C11_7
#define	ICC_SRE_ELx_SRE_BIT   BIT(0)
#define	ICC_SRE_ELx_DFB_BIT   BIT(1)
#define	ICC_SRE_ELx_DIB_BIT   BIT(2)
#define	ICC_SRE_EL3_EN_BIT   BIT(3)
#define	SGIR_TGT_MASK   (0xffff)
#define	SGIR_AFF1_SHIFT   (16)
#define	SGIR_AFF2_SHIFT   (32)
#define	SGIR_AFF3_SHIFT   (48)
#define	SGIR_AFF_MASK   (0xff)
#define	SGIR_INTID_SHIFT   (24)
#define	SGIR_INTID_MASK   (0xf)
#define	SGIR_IRM_SHIFT   (40)
#define	SGIR_IRM_MASK   (0x1)
#define	SGIR_IRM_TO_AFF   (0)
#define	GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt)
#define	L1_CACHE_SHIFT   (6)
#define	L1_CACHE_BYTES   BIT(L1_CACHE_SHIFT)
#define	ARM64_CPU_INIT_SIZE   L1_CACHE_BYTES

Macro Definition Documentation

ACTLR_EL3_CPUACTLR_BIT

#define ACTLR_EL3_CPUACTLR_BIT   BIT(0)

ACTLR_EL3_CPUECTLR_BIT

#define ACTLR_EL3_CPUECTLR_BIT   BIT(1)

ACTLR_EL3_L2ACTLR_BIT

#define ACTLR_EL3_L2ACTLR_BIT   BIT(6)

ACTLR_EL3_L2CTLR_BIT

#define ACTLR_EL3_L2CTLR_BIT   BIT(4)

ACTLR_EL3_L2ECTLR_BIT

#define ACTLR_EL3_L2ECTLR_BIT   BIT(5)

ARM64_CPU_INIT_SIZE

#define ARM64_CPU_INIT_SIZE   L1_CACHE_BYTES

CNTV_CTL_ENABLE_BIT

#define CNTV_CTL_ENABLE_BIT   BIT(0)

CNTV_CTL_IMASK_BIT

#define CNTV_CTL_IMASK_BIT   BIT(1)

CPACR_EL1_FPEN

#define CPACR_EL1_FPEN   GENMASK(21, 20)

CPACR_EL1_ZEN

#define CPACR_EL1_ZEN   GENMASK(17, 16)

CPTR_EL2_RES1

#define CPTR_EL2_RES1   BIT(13) | BIT(12) | BIT(9) | (0xff)

CPTR_EL2_TZ_BIT

#define CPTR_EL2_TZ_BIT   BIT(8)

CPTR_EL2_ZEN_EL0_EN

#define CPTR_EL2_ZEN_EL0_EN   BIT(17)

CPTR_EL2_ZEN_EL1_EN

#define CPTR_EL2_ZEN_EL1_EN   BIT(16)

CPTR_EL2_ZEN_MASK

#define CPTR_EL2_ZEN_MASK   (0x3 << CPTR_EL2_ZEN_SHIFT)

CPTR_EL2_ZEN_SHIFT

#define CPTR_EL2_ZEN_SHIFT   16

CPTR_EZ_BIT

#define CPTR_EZ_BIT   BIT(8)

CPTR_TCPAC_BIT

#define CPTR_TCPAC_BIT   BIT(31)

CPTR_TFP_BIT

#define CPTR_TFP_BIT   BIT(10)

CPTR_TTA_BIT

#define CPTR_TTA_BIT   BIT(20)

DAIF_ABT_BIT

#define DAIF_ABT_BIT   BIT(8)

DAIF_DBG_BIT

#define DAIF_DBG_BIT   BIT(9)

DAIF_FIQ_BIT

#define DAIF_FIQ_BIT   BIT(6)

DAIF_IRQ_BIT

#define DAIF_IRQ_BIT   BIT(7)

DAIFCLR_ABT_BIT

#define DAIFCLR_ABT_BIT   BIT(2)

DAIFCLR_DBG_BIT

#define DAIFCLR_DBG_BIT   BIT(3)

DAIFCLR_FIQ_BIT

#define DAIFCLR_FIQ_BIT   BIT(0)

DAIFCLR_IRQ_BIT

#define DAIFCLR_IRQ_BIT   BIT(1)

DAIFSET_ABT_BIT

#define DAIFSET_ABT_BIT   BIT(2)

DAIFSET_DBG_BIT

#define DAIFSET_DBG_BIT   BIT(3)

DAIFSET_FIQ_BIT

#define DAIFSET_FIQ_BIT   BIT(0)

DAIFSET_IRQ_BIT

#define DAIFSET_IRQ_BIT   BIT(1)

ESR_EC_MASK

#define ESR_EC_MASK   BIT_MASK(6)

ESR_EC_SHIFT

#define ESR_EC_SHIFT   (26)

ESR_IL_MASK

#define ESR_IL_MASK   BIT_MASK(1)

ESR_IL_SHIFT

#define ESR_IL_SHIFT   (25)

ESR_ISS_MASK

#define ESR_ISS_MASK   BIT_MASK(25)

ESR_ISS_SHIFT

#define ESR_ISS_SHIFT   (0)

GET_EL

#define GET_EL

(

_mode

)

Value:

(((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)

GET_ESR_EC

#define GET_ESR_EC

(

esr

)

Value:

(((esr) >> ESR_EC_SHIFT) & ESR_EC_MASK)

GET_ESR_IL

#define GET_ESR_IL

(

esr

)

Value:

(((esr) >> ESR_IL_SHIFT) & ESR_IL_MASK)

GET_ESR_ISS

#define GET_ESR_ISS

(

esr

)

Value:

(((esr) >> ESR_ISS_SHIFT) & ESR_ISS_MASK)

GET_MPIDR

#define GET_MPIDR

(

)

Value:

read_sysreg(mpidr_el1)

GICV3_SGIR_VALUE

#define GICV3_SGIR_VALUE	(		_aff3,
			_aff2,
			_aff1,
			_intid,
			_irm,
			_tgt )

Value:

        ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) |        \
         (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) |   \
         (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) |        \
         (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) |            \
         (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) |           \
         ((_tgt) & SGIR_TGT_MASK))

HCR_AMO_BIT

#define HCR_AMO_BIT   BIT(5)

HCR_FMO_BIT

#define HCR_FMO_BIT   BIT(3)

HCR_IMO_BIT

#define HCR_IMO_BIT   BIT(4)

HCR_RW_BIT

#define HCR_RW_BIT   BIT(31)

HCR_TGE_BIT

#define HCR_TGE_BIT   BIT(27)

ICC_CTLR_EL1

#define ICC_CTLR_EL1   S3_0_C12_C12_4

ICC_CTLR_EL3

#define ICC_CTLR_EL3   S3_6_C12_C12_4

ICC_EOIR0_EL1

#define ICC_EOIR0_EL1   S3_0_C12_C8_1

ICC_EOIR1_EL1

#define ICC_EOIR1_EL1   S3_0_C12_C12_1

ICC_HPPIR0_EL1

#define ICC_HPPIR0_EL1   S3_0_C12_C8_2

ICC_HPPIR1_EL1

#define ICC_HPPIR1_EL1   S3_0_C12_C12_2

ICC_IAR0_EL1

#define ICC_IAR0_EL1   S3_0_C12_C8_0

ICC_IAR1_EL1

#define ICC_IAR1_EL1   S3_0_C12_C12_0

ICC_IGRPEN0_EL1

#define ICC_IGRPEN0_EL1   S3_0_C12_C12_6

ICC_IGRPEN1_EL1

#define ICC_IGRPEN1_EL1   S3_0_C12_C12_7

ICC_IGRPEN1_EL3

#define ICC_IGRPEN1_EL3   S3_6_C12_C12_7

ICC_PMR_EL1

#define ICC_PMR_EL1   S3_0_C4_C6_0

ICC_RPR_EL1

#define ICC_RPR_EL1   S3_0_C12_C11_3

ICC_SGI0R_EL1

#define ICC_SGI0R_EL1   S3_0_C12_C11_7

ICC_SGI1R

#define ICC_SGI1R   S3_0_C12_C11_5

ICC_SRE_EL1

#define ICC_SRE_EL1   S3_0_C12_C12_5

ICC_SRE_EL2

#define ICC_SRE_EL2   S3_4_C12_C9_5

ICC_SRE_EL3

#define ICC_SRE_EL3   S3_6_C12_C12_5

ICC_SRE_EL3_EN_BIT

#define ICC_SRE_EL3_EN_BIT   BIT(3)

ICC_SRE_ELx_DFB_BIT

#define ICC_SRE_ELx_DFB_BIT   BIT(1)

ICC_SRE_ELx_DIB_BIT

#define ICC_SRE_ELx_DIB_BIT   BIT(2)

ICC_SRE_ELx_SRE_BIT

#define ICC_SRE_ELx_SRE_BIT   BIT(0)

ID_AA64PFR0_ADVSIMD_MASK

#define ID_AA64PFR0_ADVSIMD_MASK   (0xf)

ID_AA64PFR0_ADVSIMD_SHIFT

#define ID_AA64PFR0_ADVSIMD_SHIFT   (20)

ID_AA64PFR0_EL0_SHIFT

#define ID_AA64PFR0_EL0_SHIFT   (0)

ID_AA64PFR0_EL1_SHIFT

#define ID_AA64PFR0_EL1_SHIFT   (4)

ID_AA64PFR0_EL2_SHIFT

#define ID_AA64PFR0_EL2_SHIFT   (8)

ID_AA64PFR0_EL3_SHIFT

#define ID_AA64PFR0_EL3_SHIFT   (12)

ID_AA64PFR0_ELX_MASK

#define ID_AA64PFR0_ELX_MASK   (0xf)

ID_AA64PFR0_FP_MASK

#define ID_AA64PFR0_FP_MASK   (0xf)

ID_AA64PFR0_FP_SHIFT

#define ID_AA64PFR0_FP_SHIFT   (16)

ID_AA64PFR0_SEL2_MASK

#define ID_AA64PFR0_SEL2_MASK   (0xf)

ID_AA64PFR0_SEL2_SHIFT

#define ID_AA64PFR0_SEL2_SHIFT   (36)

ID_AA64PFR0_SVE_MASK

#define ID_AA64PFR0_SVE_MASK   (0xf)

ID_AA64PFR0_SVE_SHIFT

#define ID_AA64PFR0_SVE_SHIFT   (32)

L1_CACHE_BYTES

#define L1_CACHE_BYTES   BIT(L1_CACHE_SHIFT)

L1_CACHE_SHIFT

#define L1_CACHE_SHIFT   (6)

MODE_EL0

#define MODE_EL0   (0x0)

MODE_EL1

#define MODE_EL1   (0x1)

MODE_EL2

#define MODE_EL2   (0x2)

MODE_EL3

#define MODE_EL3   (0x3)

MODE_EL_MASK

#define MODE_EL_MASK   (0x3)

MODE_EL_SHIFT

#define MODE_EL_SHIFT   (0x2)

MPIDR_AFF0_SHIFT

#define MPIDR_AFF0_SHIFT   (0)

MPIDR_AFF1_SHIFT

#define MPIDR_AFF1_SHIFT   (8)

MPIDR_AFF2_SHIFT

#define MPIDR_AFF2_SHIFT   (16)

MPIDR_AFF3_SHIFT

#define MPIDR_AFF3_SHIFT   (32)

MPIDR_AFF_MASK

#define MPIDR_AFF_MASK   (GENMASK(23, 0) | GENMASK(39, 32))

MPIDR_AFFLVL

#define MPIDR_AFFLVL	(		mpidr,
			aff_level )

Value:

                (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)

MPIDR_AFFLVL_MASK

#define MPIDR_AFFLVL_MASK   (0xffULL)

MPIDR_TO_CORE

#define MPIDR_TO_CORE

(

mpidr

)

Value:

(mpidr & MPIDR_AFF_MASK)

SCR_EA_BIT

#define SCR_EA_BIT   BIT(3)

SCR_EEL2_BIT

#define SCR_EEL2_BIT   BIT(18)

SCR_FIQ_BIT

#define SCR_FIQ_BIT   BIT(2)

SCR_HCE_BIT

#define SCR_HCE_BIT   BIT(8)

SCR_IRQ_BIT

#define SCR_IRQ_BIT   BIT(1)

SCR_NS_BIT

#define SCR_NS_BIT   BIT(0)

SCR_RES1

#define SCR_RES1   (BIT(4) | BIT(5))

SCR_RW_BIT

#define SCR_RW_BIT   BIT(10)

SCR_SMD_BIT

#define SCR_SMD_BIT   BIT(7)

SCR_ST_BIT

#define SCR_ST_BIT   BIT(11)

SCTLR_A_BIT

#define SCTLR_A_BIT   BIT(1)

SCTLR_BR_BIT

#define SCTLR_BR_BIT   BIT(17)

SCTLR_C_BIT

#define SCTLR_C_BIT   BIT(2)

SCTLR_EL1_RES1

#define SCTLR_EL1_RES1

Value:

                                 (BIT(29) | BIT(28) | BIT(23) | \
                                 BIT(22) | BIT(20) | BIT(11))

SCTLR_EL2_RES1

#define SCTLR_EL2_RES1

Value:

                                 (BIT(29) | BIT(28) | BIT(23) | \
                                 BIT(22) | BIT(18) | BIT(16) | \
                                 BIT(11) | BIT(5)  | BIT(4))

SCTLR_EL3_RES1

#define SCTLR_EL3_RES1

Value:

                                 (BIT(29) | BIT(28) | BIT(23) | \
                                 BIT(22) | BIT(18) | BIT(16) | \
                                 BIT(11) | BIT(5)  | BIT(4))

SCTLR_I_BIT

#define SCTLR_I_BIT   BIT(12)

SCTLR_M_BIT

#define SCTLR_M_BIT   BIT(0)

SCTLR_SA_BIT

#define SCTLR_SA_BIT   BIT(3)

SGIR_AFF1_SHIFT

#define SGIR_AFF1_SHIFT   (16)

SGIR_AFF2_SHIFT

#define SGIR_AFF2_SHIFT   (32)

SGIR_AFF3_SHIFT

#define SGIR_AFF3_SHIFT   (48)

SGIR_AFF_MASK

#define SGIR_AFF_MASK   (0xff)

SGIR_INTID_MASK

#define SGIR_INTID_MASK   (0xf)

SGIR_INTID_SHIFT

#define SGIR_INTID_SHIFT   (24)

SGIR_IRM_MASK

#define SGIR_IRM_MASK   (0x1)

SGIR_IRM_SHIFT

#define SGIR_IRM_SHIFT   (40)

SGIR_IRM_TO_AFF

#define SGIR_IRM_TO_AFF   (0)

SGIR_TGT_MASK

#define SGIR_TGT_MASK   (0xffff)

SPSR_DAIF_MASK

#define SPSR_DAIF_MASK   (0xf << SPSR_DAIF_SHIFT)

SPSR_DAIF_SHIFT

#define SPSR_DAIF_SHIFT   (6)

SPSR_MODE_EL0T

#define SPSR_MODE_EL0T   (0x0)

SPSR_MODE_EL1H

#define SPSR_MODE_EL1H   (0x5)

SPSR_MODE_EL1T

#define SPSR_MODE_EL1T   (0x4)

SPSR_MODE_EL2H

#define SPSR_MODE_EL2H   (0x9)

SPSR_MODE_EL2T

#define SPSR_MODE_EL2T   (0x8)

SPSR_MODE_MASK

#define SPSR_MODE_MASK   (0xf)

ZCR_EL1

#define ZCR_EL1   S3_0_C1_C2_0

ZCR_EL2

#define ZCR_EL2   S3_4_C1_C2_0

ZCR_EL3

#define ZCR_EL3   S3_6_C1_C2_0