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Zephyr API Documentation 4.4.0-rc1
A Scalable Open Source RTOS
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Clock IDs for the BL70XL SoC series. More...
#include "bflb_clock_common.h"Go to the source code of this file.
Macros | |
| #define | BL70XL_CLKID_CLK_ROOT BFLB_CLKID_CLK_ROOT |
| Root Clock. | |
| #define | BL70XL_CLKID_CLK_RC32M BFLB_CLKID_CLK_RC32M |
| 32MHz RC Oscillator Clock | |
| #define | BL70XL_CLKID_CLK_CRYSTAL BFLB_CLKID_CLK_CRYSTAL |
| Crystal as clock. | |
| #define | BL70XL_CLKID_CLK_BCLK BFLB_CLKID_CLK_BCLK |
| Bus Clock. | |
| #define | BL70XL_CLKID_CLK_F32K BFLB_CLKID_CLK_F32K |
| F32K Clock. | |
| #define | BL70XL_CLKID_CLK_XTAL32K BFLB_CLKID_CLK_XTAL32K |
| XTAL32K Clock. | |
| #define | BL70XL_CLKID_CLK_RC32K BFLB_CLKID_CLK_RC32K |
| RC32K Clock. | |
| #define | BL70XL_CLKID_CLK_DLL BFLB_CLKID_CLK_PRIVATE |
| DLL clock, the standard root frequency of the DLL is 128MHz. | |
| #define | BL70XL_DLL_25P6MHZ 0 |
| ID 0, DLL 25.6MHz output. | |
| #define | BL70XL_DLL_42P67MHZ 1 |
| ID 1, DLL 42.67MHz output. | |
| #define | BL70XL_DLL_64MHZ 2 |
| ID 2, DLL 64MHz output. | |
| #define | BL70XL_DLL_128MHZ 3 |
| ID 3, DLL 128MHz output. | |
Clock IDs for the BL70XL SoC series.
| #define BL70XL_CLKID_CLK_BCLK BFLB_CLKID_CLK_BCLK |
Bus Clock.
| #define BL70XL_CLKID_CLK_CRYSTAL BFLB_CLKID_CLK_CRYSTAL |
Crystal as clock.
| #define BL70XL_CLKID_CLK_DLL BFLB_CLKID_CLK_PRIVATE |
DLL clock, the standard root frequency of the DLL is 128MHz.
| #define BL70XL_CLKID_CLK_F32K BFLB_CLKID_CLK_F32K |
F32K Clock.
| #define BL70XL_CLKID_CLK_RC32K BFLB_CLKID_CLK_RC32K |
RC32K Clock.
| #define BL70XL_CLKID_CLK_RC32M BFLB_CLKID_CLK_RC32M |
32MHz RC Oscillator Clock
| #define BL70XL_CLKID_CLK_ROOT BFLB_CLKID_CLK_ROOT |
Root Clock.
| #define BL70XL_CLKID_CLK_XTAL32K BFLB_CLKID_CLK_XTAL32K |
XTAL32K Clock.
| #define BL70XL_DLL_128MHZ 3 |
ID 3, DLL 128MHz output.
| #define BL70XL_DLL_25P6MHZ 0 |
ID 0, DLL 25.6MHz output.
| #define BL70XL_DLL_42P67MHZ 1 |
ID 1, DLL 42.67MHz output.
| #define BL70XL_DLL_64MHZ 2 |
ID 2, DLL 64MHz output.