bflb_bl808_clock.h File Reference

BL808 clock IDs and PLL configuration constants for device tree bindings. More...

#include "bflb_clock_common.h"

Go to the source code of this file.

Macros
#define	BL808_CLKID_CLK_ROOT   BFLB_CLKID_CLK_ROOT
	Root Clock.
#define	BL808_CLKID_CLK_RC32M   BFLB_CLKID_CLK_RC32M
	32MHz RC Oscillator Clock
#define	BL808_CLKID_CLK_CRYSTAL   BFLB_CLKID_CLK_CRYSTAL
	Crystal Clock.
#define	BL808_CLKID_CLK_BCLK   BFLB_CLKID_CLK_BCLK
	Bus Clock.
#define	BL808_CLKID_CLK_F32K   BFLB_CLKID_CLK_F32K
	F32K Clock.
#define	BL808_CLKID_CLK_XTAL32K   BFLB_CLKID_CLK_XTAL32K
	XTAL32K Clock.
#define	BL808_CLKID_CLK_RC32K   BFLB_CLKID_CLK_RC32K
	RC32K Clock.
#define	BL808_CLKID_CLK_WIFIPLL   (BFLB_CLKID_CLK_PRIVATE + 0)
	WiFi PLL Clock.
#define	BL808_CLKID_CLK_AUPLL   (BFLB_CLKID_CLK_PRIVATE + 1)
	Audio PLL Clock.
#define	BL808_CLKID_CLK_CPUPLL   (BFLB_CLKID_CLK_PRIVATE + 2)
	CPU PLL Clock.
#define	BL808_CLKID_CLK_160M   (BFLB_CLKID_CLK_PRIVATE + 3)
	160MHz Clock
#define	BL808_CPUPLL_ID_400M   0
	CPU PLL output select: top frequency (400 MHz).
#define	BL808_AUPLL_ID_DIV1   1
	AUPLL output select: divide by 1.
#define	BL808_WIFIPLL_ID_DIV3_4   2
	WiFi PLL output select: 3/4 of top frequency.
#define	BL808_WIFIPLL_ID_DIV1   3
	WiFi PLL output select: top frequency.
#define	BL808_WIFIPLL_TOP_FREQ   DT_FREQ_M(320)
	WiFi PLL top frequency (960MHz VCO / 3 = 320MHz).
#define	BL808_AUPLL_TOP_FREQ   DT_FREQ_M(1)
	Audio PLL top frequency.
#define	BL808_WIFIPLL_TOP_FREQ_OC1   DT_FREQ_M(480)
	Overclocked WiFi PLL top frequency (960MHz VCO / 2 = 480MHz).
#define	BL808_WIFIPLL_TOP_FREQ_OC2   DT_FREQ_M(640)
	Overclocked WiFi PLL top frequency (no divider = 640MHz).
#define	BL808_CPUPLL_TOP_FREQ   DT_FREQ_M(400)
	CPU PLL top frequency (800 MHz VCO / 2 = 400 MHz).

Detailed Description

BL808 clock IDs and PLL configuration constants for device tree bindings.

Macro Definition Documentation

BL808_AUPLL_ID_DIV1

#define BL808_AUPLL_ID_DIV1   1

AUPLL output select: divide by 1.

BL808_AUPLL_TOP_FREQ

#define BL808_AUPLL_TOP_FREQ   DT_FREQ_M(1)

Audio PLL top frequency.

BL808_CLKID_CLK_160M

#define BL808_CLKID_CLK_160M   (BFLB_CLKID_CLK_PRIVATE + 3)

160MHz Clock

BL808_CLKID_CLK_AUPLL

#define BL808_CLKID_CLK_AUPLL   (BFLB_CLKID_CLK_PRIVATE + 1)

Audio PLL Clock.

BL808_CLKID_CLK_BCLK

#define BL808_CLKID_CLK_BCLK   BFLB_CLKID_CLK_BCLK

Bus Clock.

BL808_CLKID_CLK_CPUPLL

#define BL808_CLKID_CLK_CPUPLL   (BFLB_CLKID_CLK_PRIVATE + 2)

CPU PLL Clock.

BL808_CLKID_CLK_CRYSTAL

#define BL808_CLKID_CLK_CRYSTAL   BFLB_CLKID_CLK_CRYSTAL

Crystal Clock.

BL808_CLKID_CLK_F32K

#define BL808_CLKID_CLK_F32K   BFLB_CLKID_CLK_F32K

F32K Clock.

BL808_CLKID_CLK_RC32K

#define BL808_CLKID_CLK_RC32K   BFLB_CLKID_CLK_RC32K

RC32K Clock.

BL808_CLKID_CLK_RC32M

#define BL808_CLKID_CLK_RC32M   BFLB_CLKID_CLK_RC32M

32MHz RC Oscillator Clock

BL808_CLKID_CLK_ROOT

#define BL808_CLKID_CLK_ROOT   BFLB_CLKID_CLK_ROOT

Root Clock.

BL808_CLKID_CLK_WIFIPLL

#define BL808_CLKID_CLK_WIFIPLL   (BFLB_CLKID_CLK_PRIVATE + 0)

WiFi PLL Clock.

BL808_CLKID_CLK_XTAL32K

#define BL808_CLKID_CLK_XTAL32K   BFLB_CLKID_CLK_XTAL32K

XTAL32K Clock.

BL808_CPUPLL_ID_400M

#define BL808_CPUPLL_ID_400M   0

CPU PLL output select: top frequency (400 MHz).

BL808_CPUPLL_TOP_FREQ

#define BL808_CPUPLL_TOP_FREQ   DT_FREQ_M(400)

CPU PLL top frequency (800 MHz VCO / 2 = 400 MHz).

BL808_WIFIPLL_ID_DIV1

#define BL808_WIFIPLL_ID_DIV1   3

WiFi PLL output select: top frequency.

BL808_WIFIPLL_ID_DIV3_4

#define BL808_WIFIPLL_ID_DIV3_4   2

WiFi PLL output select: 3/4 of top frequency.

BL808_WIFIPLL_TOP_FREQ

#define BL808_WIFIPLL_TOP_FREQ   DT_FREQ_M(320)

WiFi PLL top frequency (960MHz VCO / 3 = 320MHz).

BL808_WIFIPLL_TOP_FREQ_OC1

#define BL808_WIFIPLL_TOP_FREQ_OC1   DT_FREQ_M(480)

Overclocked WiFi PLL top frequency (960MHz VCO / 2 = 480MHz).

BL808_WIFIPLL_TOP_FREQ_OC2

#define BL808_WIFIPLL_TOP_FREQ_OC2   DT_FREQ_M(640)

Overclocked WiFi PLL top frequency (no divider = 640MHz).