|
| #define | CH32V20X_V30X_PINMUX_PORT_PA 0 |
| #define | CH32V20X_V30X_PINMUX_PORT_PB 1 |
| #define | CH32V20X_V30X_PINMUX_PORT_PC 2 |
| #define | CH32V20X_V30X_PINMUX_PORT_PD 3 |
| #define | CH32V20X_V30X_PINMUX_PORT_PE 4 |
| #define | CH32V20X_V30X_PINMUX_SPI1_RM 0 |
| #define | CH32V20X_V30X_PINMUX_I2C1_RM 1 |
| #define | CH32V20X_V30X_PINMUX_USART1_RM 2 |
| #define | CH32V20X_V30X_PINMUX_USART2_RM 3 |
| #define | CH32V20X_V30X_PINMUX_USART3_RM 4 |
| #define | CH32V20X_V30X_PINMUX_TIM1_RM 6 |
| #define | CH32V20X_V30X_PINMUX_TIM2_RM 8 |
| #define | CH32V20X_V30X_PINMUX_TIM3_RM 10 |
| #define | CH32V20X_V30X_PINMUX_TIM4_RM 12 |
| #define | CH32V20X_V30X_PINMUX_CAN1_RM 13 |
| #define | CH32V20X_V30X_PINMUX_PD01_RM 15 |
| #define | CH32V20X_V30X_PINMUX_TIM5CH4_RM 16 |
| #define | CH32V20X_V30X_PINMUX_ETH_RM 21 |
| #define | CH32V20X_V30X_PINMUX_CAN2_RM 22 |
| #define | CH32V20X_V30X_PINMUX_RMII_RM 23 |
| #define | CH32V20X_V30X_PINMUX_SDI_RM 24 |
| #define | CH32V20X_V30X_PINMUX_I2C2_RM 0 |
| | I2C2 remap bit position in PCFR2.
|
| #define | CH32V20X_V30X_PINMUX_SPI2_RM 0 |
| | SPI2 remap bit position in PCFR2.
|
| #define | CH32V20X_V30X_PINMUX_SPI3_RM 28 |
| #define | CH32V20X_V30X_PINMUX_TIM8_RM (32 + 2) |
| #define | CH32V20X_V30X_PINMUX_TIM9_RM (32 + 3) |
| #define | CH32V20X_V30X_PINMUX_TIM10_RM (32 + 5) |
| #define | CH32V20X_V30X_PINMUX_USART4_RM (32 + 16) |
| #define | CH32V20X_V30X_PINMUX_USART5_RM (32 + 18) |
| #define | CH32V20X_V30X_PINMUX_USART6_RM (32 + 20) |
| #define | CH32V20X_V30X_PINMUX_USART7_RM (32 + 22) |
| #define | CH32V20X_V30X_PINMUX_USART8_RM (32 + 24) |
| #define | CH32V20X_V30X_PINMUX_USART1_RM1 (32 + 26) |
| #define | CH32V20X_V30X_PINCTRL_PORT_SHIFT 0 |
| #define | CH32V20X_V30X_PINCTRL_PORT_MASK GENMASK(2, 0) |
| #define | CH32V20X_V30X_PINCTRL_PIN_SHIFT 3 |
| #define | CH32V20X_V30X_PINCTRL_PIN_MASK GENMASK(6, 3) |
| #define | CH32V20X_V30X_PINCTRL_RM_BASE_SHIFT 7 |
| #define | CH32V20X_V30X_PINCTRL_RM_BASE_MASK GENMASK(11, 7) |
| #define | CH32V20X_V30X_PINCTRL_PCFR_ID_SHIFT 12 |
| #define | CH32V20X_V30X_PINCTRL_PCFR_ID_MASK GENMASK(12, 12) |
| #define | CH32V20X_V30X_PINCTRL_RM_SHIFT 13 |
| #define | CH32V20X_V30X_PINCTRL_RM_MASK GENMASK(14, 13) |
| #define | CH32V20X_V30X_PINMUX_DEFINE(port, pin, rm, remapping) |
| #define | USART1_CK_PA8_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 0) |
| #define | USART1_CK_PA8_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 1) |
| #define | USART1_CK_PA10_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, USART1, 2) |
| #define | USART1_CK_PA5_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART1, 3) |
| #define | USART1_TX_PA9_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, USART1, 0) |
| #define | USART1_TX_PB6_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, USART1, 1) |
| #define | USART1_TX_PB15_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 15, USART1, 2) |
| #define | USART1_TX_PA6_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART1, 3) |
| #define | USART1_RX_PA10_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, USART1, 0) |
| #define | USART1_RX_PB7_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, USART1, 1) |
| #define | USART1_RX_PA8_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 2) |
| #define | USART1_RX_PA7_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART1, 3) |
| #define | USART1_CTS_PA11_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, USART1, 0) |
| #define | USART1_CTS_PA11_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, USART1, 1) |
| #define | USART1_CTS_PA5_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART1, 2) |
| #define | USART1_CTS_PC4_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 4, USART1, 3) |
| #define | USART1_RTS_PA12_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, USART1, 0) |
| #define | USART1_RTS_PA12_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, USART1, 1) |
| #define | USART1_RTS_PA9_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, USART1, 2) |
| #define | USART1_RTS_PC5_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 5, USART1, 3) |
| #define | USART2_CK_PA4_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, USART2, 0) |
| #define | USART2_CK_PD7_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 7, USART2, 1) |
| #define | USART2_TX_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, USART2, 0) |
| #define | USART2_TX_PD5_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 5, USART2, 1) |
| #define | USART2_RX_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, USART2, 0) |
| #define | USART2_RX_PD6_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 6, USART2, 1) |
| #define | USART2_CTS_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, USART2, 0) |
| #define | USART2_CTS_PD3_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 3, USART2, 1) |
| #define | USART2_RTS_PA1_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, USART2, 0) |
| #define | USART2_RTS_PD4_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 4, USART2, 1) |
| #define | USART3_CK_PB12_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 12, USART3, 0) |
| #define | USART3_CK_PC12_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, USART3, 1) |
| #define | USART3_CK_PD10_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 10, USART3, 2) |
| #define | USART3_CK_PD10_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 10, USART3, 3) |
| #define | USART3_TX_PB10_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, USART3, 0) |
| #define | USART3_TX_PC10_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 10, USART3, 1) |
| #define | USART3_TX_PA13_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 13, USART3, 2) |
| #define | USART3_TX_PD8_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 8, USART3, 3) |
| #define | USART3_RX_PB11_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, USART3, 0) |
| #define | USART3_RX_PC11_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 11, USART3, 1) |
| #define | USART3_RX_PA14_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, USART3, 2) |
| #define | USART3_RX_PD9_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 9, USART3, 3) |
| #define | USART3_CTS_PB13_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, USART3, 0) |
| #define | USART3_CTS_PB13_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, USART3, 1) |
| #define | USART3_CTS_PD11_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, USART3, 2) |
| #define | USART3_CTS_PD11_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, USART3, 3) |
| #define | USART3_RTS_PB14_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, USART3, 0) |
| #define | USART3_RTS_PB14_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, USART3, 1) |
| #define | USART3_RTS_PD12_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, USART3, 2) |
| #define | USART3_RTS_PD12_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, USART3, 3) |
| #define | USART4_CK_PB2_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 2, USART4, 0) |
| #define | USART4_CK_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART4, 1) |
| #define | USART4_TX_PB0_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, USART4, 0) |
| #define | USART4_TX_PA5_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART4, 1) |
| #define | USART4_RX_PB1_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, USART4, 0) |
| #define | USART4_RX_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, USART4, 1) |
| #define | USART4_CTS_PB3_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, USART4, 0) |
| #define | USART4_CTS_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART4, 1) |
| #define | USART4_RTS_PB4_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, USART4, 0) |
| #define | USART4_RTS_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, USART4, 1) |
| #define | USART5_TX_PC12_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, USART5, 0) |
| #define | USART5_TX_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, USART5, 1) |
| #define | USART5_TX_PE8_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 8, USART5, 2) |
| #define | USART5_RX_PD2_0 CH32V20X_V30X_PINMUX_DEFINE(PD, 2, USART5, 0) |
| #define | USART5_RX_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, USART5, 1) |
| #define | USART5_RX_PE9_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 9, USART5, 2) |
| #define | USART6_TX_PC0_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 0, USART6, 0) |
| #define | USART6_TX_PB8_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, USART6, 1) |
| #define | USART6_TX_PE10_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 10, USART6, 2) |
| #define | USART6_RX_PC1_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 1, USART6, 0) |
| #define | USART6_RX_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, USART6, 1) |
| #define | USART6_RX_PE11_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 11, USART6, 2) |
| #define | USART7_TX_PC2_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 2, USART7, 0) |
| #define | USART7_TX_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART7, 1) |
| #define | USART7_TX_PE12_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 12, USART7, 2) |
| #define | USART7_RX_PC3_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 3, USART7, 0) |
| #define | USART7_RX_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART7, 1) |
| #define | USART7_RX_PE13_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 13, USART7, 2) |
| #define | USART8_TX_PC4_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 4, USART8, 0) |
| #define | USART8_TX_PA14_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, USART8, 1) |
| #define | USART8_TX_PE14_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 14, USART8, 2) |
| #define | USART8_RX_PC5_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 5, USART8, 0) |
| #define | USART8_RX_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, USART8, 1) |
| #define | USART8_RX_PE15_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 15, USART8, 2) |
| #define | SPI1_NSS_PA4_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, SPI1, 0) |
| #define | SPI1_NSS_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, SPI1, 1) |
| #define | SPI1_SCK_PA5_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, SPI1, 0) |
| #define | SPI1_SCK_PB3_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, SPI1, 1) |
| #define | SPI1_MISO_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, SPI1, 0) |
| #define | SPI1_MISO_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, SPI1, 1) |
| #define | SPI1_MOSI_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, SPI1, 0) |
| #define | SPI1_MOSI_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, SPI1, 1) |
| #define | I2C1_SCL_PB6_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, I2C1, 0) |
| #define | I2C1_SCL_PB8_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, I2C1, 1) |
| #define | I2C1_SDA_PB7_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, I2C1, 0) |
| #define | I2C1_SDA_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, I2C1, 1) |
| #define | I2C2_SCL_PB10_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, I2C2, 0) |
| | I2C2 SCL on PB10, no remap.
|
| #define | I2C2_SDA_PB11_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, I2C2, 0) |
| | I2C2 SDA on PB11, no remap.
|
| #define | SPI2_NSS_PB12_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 12, SPI2, 0) |
| #define | SPI2_SCK_PB13_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, SPI2, 0) |
| #define | SPI2_MISO_PB14_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, SPI2, 0) |
| #define | SPI2_MOSI_PB15_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 15, SPI2, 0) |
| #define | SPI3_NSS_PA15_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, SPI3, 0) |
| #define | SPI3_NSS_PA4_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, SPI3, 1) |
| #define | SPI3_SCK_PB3_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, SPI3, 0) |
| #define | SPI3_SCK_PC10_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 10, SPI3, 1) |
| #define | SPI3_MISO_PB4_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, SPI3, 0) |
| #define | SPI3_MISO_PC11_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 11, SPI3, 1) |
| #define | SPI3_MOSI_PB5_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, SPI3, 0) |
| #define | SPI3_MOSI_PC12_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, SPI3, 1) |
| #define | TIM1_ETR_PA12_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, TIM1, 0) |
| | TIM1_ETR on PA12.
|
| #define | TIM1_ETR_PA12_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, TIM1, 1) |
| | TIM1_ETR on PA12.
|
| #define | TIM1_ETR_PE7_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 7, TIM1, 3) |
| | TIM1_ETR on PE7.
|
| #define | TIM1_CH1_PA8_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, TIM1, 0) |
| | TIM1_CH1 on PA8.
|
| #define | TIM1_CH1_PA8_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, TIM1, 1) |
| | TIM1_CH1 on PA8.
|
| #define | TIM1_CH1_PE9_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 9, TIM1, 3) |
| | TIM1_CH1 on PE9.
|
| #define | TIM1_CH2_PA9_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, TIM1, 0) |
| | TIM1_CH2 on PA9.
|
| #define | TIM1_CH2_PA9_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, TIM1, 1) |
| | TIM1_CH2 on PA9.
|
| #define | TIM1_CH2_PE11_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 11, TIM1, 3) |
| | TIM1_CH2 on PE11.
|
| #define | TIM1_CH3_PA10_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, TIM1, 0) |
| | TIM1_CH3 on PA10.
|
| #define | TIM1_CH3_PA10_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, TIM1, 1) |
| | TIM1_CH3 on PA10.
|
| #define | TIM1_CH3_PE13_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 13, TIM1, 3) |
| | TIM1_CH3 on PE13.
|
| #define | TIM1_CH4_PA11_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, TIM1, 0) |
| | TIM1_CH4 on PA11.
|
| #define | TIM1_CH4_PA11_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, TIM1, 1) |
| | TIM1_CH4 on PA11.
|
| #define | TIM1_CH4_PE14_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 14, TIM1, 3) |
| | TIM1_CH4 on PE14.
|
| #define | TIM1_BKIN_PB12_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 12, TIM1, 0) |
| | TIM1_BKIN on PB12.
|
| #define | TIM1_BKIN_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM1, 1) |
| | TIM1_BKIN on PA6.
|
| #define | TIM1_BKIN_PE15_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 15, TIM1, 3) |
| | TIM1_BKIN on PE15.
|
| #define | TIM1_CH1N_PB13_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, TIM1, 0) |
| | TIM1_CH1N on PB13.
|
| #define | TIM1_CH1N_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM1, 1) |
| | TIM1_CH1N on PA7.
|
| #define | TIM1_CH1N_PE8_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 8, TIM1, 3) |
| | TIM1_CH1N on PE8.
|
| #define | TIM1_CH2N_PB14_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, TIM1, 0) |
| | TIM1_CH2N on PB14.
|
| #define | TIM1_CH2N_PB0_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM1, 1) |
| | TIM1_CH2N on PB0.
|
| #define | TIM1_CH2N_PE10_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 10, TIM1, 3) |
| | TIM1_CH2N on PE10.
|
| #define | TIM1_CH3N_PB15_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 15, TIM1, 0) |
| | TIM1_CH3N on PB15.
|
| #define | TIM1_CH3N_PB1_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM1, 1) |
| | TIM1_CH3N on PB1.
|
| #define | TIM1_CH3N_PE12_3 CH32V20X_V30X_PINMUX_DEFINE(PE, 12, TIM1, 3) |
| | TIM1_CH3N on PE12.
|
| #define | TIM2_ETR_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 0) |
| | TIM2_ETR on PA0.
|
| #define | TIM2_ETR_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 1) |
| | TIM2_ETR on PA15.
|
| #define | TIM2_ETR_PA0_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 2) |
| | TIM2_ETR on PA0.
|
| #define | TIM2_ETR_PA15_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 3) |
| | TIM2_ETR on PA15.
|
| #define | TIM2_CH1_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 0) |
| | TIM2_CH1 on PA0.
|
| #define | TIM2_CH1_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 1) |
| | TIM2_CH1 on PA15.
|
| #define | TIM2_CH1_PA0_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM2, 2) |
| | TIM2_CH1 on PA0.
|
| #define | TIM2_CH1_PA15_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM2, 3) |
| | TIM2_CH1 on PA15.
|
| #define | TIM2_CH2_PA1_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, TIM2, 0) |
| | TIM2_CH2 on PA1.
|
| #define | TIM2_CH2_PB3_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, TIM2, 1) |
| | TIM2_CH2 on PB3.
|
| #define | TIM2_CH2_PA1_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, TIM2, 2) |
| | TIM2_CH2 on PA1.
|
| #define | TIM2_CH2_PB3_3 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, TIM2, 3) |
| | TIM2_CH2 on PB3.
|
| #define | TIM2_CH3_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM2, 0) |
| | TIM2_CH3 on PA2.
|
| #define | TIM2_CH3_PA2_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM2, 1) |
| | TIM2_CH3 on PA2.
|
| #define | TIM2_CH3_PB10_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, TIM2, 2) |
| | TIM2_CH3 on PB10.
|
| #define | TIM2_CH3_PB10_3 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, TIM2, 3) |
| | TIM2_CH3 on PB10.
|
| #define | TIM2_CH4_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM2, 0) |
| | TIM2_CH4 on PA3.
|
| #define | TIM2_CH4_PA3_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM2, 1) |
| | TIM2_CH4 on PA3.
|
| #define | TIM2_CH4_PB11_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, TIM2, 2) |
| | TIM2_CH4 on PB11.
|
| #define | TIM2_CH4_PB11_3 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, TIM2, 3) |
| | TIM2_CH4 on PB11.
|
| #define | TIM3_CH1_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM3, 0) |
| | TIM3_CH1 on PA6.
|
| #define | TIM3_CH1_PB4_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, TIM3, 2) |
| | TIM3_CH1 on PB4.
|
| #define | TIM3_CH1_PC6_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 6, TIM3, 3) |
| | TIM3_CH1 on PC6.
|
| #define | TIM3_CH2_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM3, 0) |
| | TIM3_CH2 on PA7.
|
| #define | TIM3_CH2_PB5_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, TIM3, 2) |
| | TIM3_CH2 on PB5.
|
| #define | TIM3_CH2_PC7_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 7, TIM3, 3) |
| | TIM3_CH2 on PC7.
|
| #define | TIM3_CH3_PB0_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM3, 0) |
| | TIM3_CH3 on PB0.
|
| #define | TIM3_CH3_PB0_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM3, 2) |
| | TIM3_CH3 on PB0.
|
| #define | TIM3_CH3_PC8_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 8, TIM3, 3) |
| | TIM3_CH3 on PC8.
|
| #define | TIM3_CH4_PB1_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM3, 0) |
| | TIM3_CH4 on PB1.
|
| #define | TIM3_CH4_PB1_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM3, 2) |
| | TIM3_CH4 on PB1.
|
| #define | TIM3_CH4_PC9_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 9, TIM3, 3) |
| | TIM3_CH4 on PC9.
|
| #define | TIM4_CH1_PB6_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, TIM4, 0) |
| | TIM4_CH1 on PB6.
|
| #define | TIM4_CH1_PD12_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, TIM4, 1) |
| | TIM4_CH1 on PD12.
|
| #define | TIM4_CH2_PB7_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, TIM4, 0) |
| | TIM4_CH2 on PB7.
|
| #define | TIM4_CH2_PD13_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 13, TIM4, 1) |
| | TIM4_CH2 on PD13.
|
| #define | TIM4_CH3_PB8_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, TIM4, 0) |
| | TIM4_CH3 on PB8.
|
| #define | TIM4_CH3_PD14_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 14, TIM4, 1) |
| | TIM4_CH3 on PD14.
|
| #define | TIM4_CH4_PB9_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, TIM4, 0) |
| | TIM4_CH4 on PB9.
|
| #define | TIM4_CH4_PD15_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 15, TIM4, 1) |
| | TIM4_CH4 on PD15.
|
| #define | TIM5_CH4_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM5CH4, 0) |
| | TIM5_CH4 on PA3.
|
| #define | TIM8_ETR_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM8, 0) |
| | TIM8_ETR on PA0.
|
| #define | TIM8_ETR_PA0_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, TIM8, 1) |
| | TIM8_ETR on PA0.
|
| #define | TIM8_CH1_PC6_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 6, TIM8, 0) |
| | TIM8_CH1 on PC6.
|
| #define | TIM8_CH1_PB6_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, TIM8, 1) |
| | TIM8_CH1 on PB6.
|
| #define | TIM8_CH2_PC7_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 7, TIM8, 0) |
| | TIM8_CH2 on PC7.
|
| #define | TIM8_CH2_PB7_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, TIM8, 1) |
| | TIM8_CH2 on PB7.
|
| #define | TIM8_CH3_PC8_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 8, TIM8, 0) |
| | TIM8_CH3 on PC8.
|
| #define | TIM8_CH3_PB8_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, TIM8, 1) |
| | TIM8_CH3 on PB8.
|
| #define | TIM8_CH4_PC9_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 9, TIM8, 0) |
| | TIM8_CH4 on PC9.
|
| #define | TIM8_CH4_PC13_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 13, TIM8, 1) |
| | TIM8_CH4 on PC13.
|
| #define | TIM8_BKIN_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM8, 0) |
| | TIM8_BKIN on PA6.
|
| #define | TIM8_BKIN_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, TIM8, 1) |
| | TIM8_BKIN on PB9.
|
| #define | TIM8_CH1N_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM8, 0) |
| | TIM8_CH1N on PA7.
|
| #define | TIM8_CH1N_PA13_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 13, TIM8, 1) |
| | TIM8_CH1N on PA13.
|
| #define | TIM8_CH2N_PB0_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM8, 0) |
| | TIM8_CH2N on PB0.
|
| #define | TIM8_CH2N_PA14_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, TIM8, 1) |
| | TIM8_CH2N on PA14.
|
| #define | TIM8_CH3N_PB1_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM8, 0) |
| | TIM8_CH3N on PB1.
|
| #define | TIM8_CH3N_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, TIM8, 1) |
| | TIM8_CH3N on PA15.
|
| #define | TIM9_ETR_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 0) |
| | TIM9_ETR on PA2.
|
| #define | TIM9_ETR_PA2_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 1) |
| | TIM9_ETR on PA2.
|
| #define | TIM9_ETR_PD9_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 9, TIM9, 2) |
| | TIM9_ETR on PD9.
|
| #define | TIM9_CH1_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 0) |
| | TIM9_CH1 on PA2.
|
| #define | TIM9_CH1_PA2_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, TIM9, 1) |
| | TIM9_CH1 on PA2.
|
| #define | TIM9_CH1_PD9_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 9, TIM9, 2) |
| | TIM9_CH1 on PD9.
|
| #define | TIM9_CH2_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM9, 0) |
| | TIM9_CH2 on PA3.
|
| #define | TIM9_CH2_PA3_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, TIM9, 1) |
| | TIM9_CH2 on PA3.
|
| #define | TIM9_CH2_PD11_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, TIM9, 2) |
| | TIM9_CH2 on PD11.
|
| #define | TIM9_CH3_PA4_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, TIM9, 0) |
| | TIM9_CH3 on PA4.
|
| #define | TIM9_CH3_PA4_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, TIM9, 1) |
| | TIM9_CH3 on PA4.
|
| #define | TIM9_CH3_PD13_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 13, TIM9, 2) |
| | TIM9_CH3 on PD13.
|
| #define | TIM9_CH4_PC4_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 4, TIM9, 0) |
| | TIM9_CH4 on PC4.
|
| #define | TIM9_CH4_PC14_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 14, TIM9, 1) |
| | TIM9_CH4 on PC14.
|
| #define | TIM9_CH4_PD15_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 15, TIM9, 2) |
| | TIM9_CH4 on PD15.
|
| #define | TIM9_BKIN_PC5_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 5, TIM9, 0) |
| | TIM9_BKIN on PC5.
|
| #define | TIM9_BKIN_PA1_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, TIM9, 1) |
| | TIM9_BKIN on PA1.
|
| #define | TIM9_BKIN_PD14_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 14, TIM9, 2) |
| | TIM9_BKIN on PD14.
|
| #define | TIM9_CH1N_PC0_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 0, TIM9, 0) |
| | TIM9_CH1N on PC0.
|
| #define | TIM9_CH1N_PB0_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, TIM9, 1) |
| | TIM9_CH1N on PB0.
|
| #define | TIM9_CH1N_PD8_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 8, TIM9, 2) |
| | TIM9_CH1N on PD8.
|
| #define | TIM9_CH2N_PC1_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 1, TIM9, 0) |
| | TIM9_CH2N on PC1.
|
| #define | TIM9_CH2N_PB1_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, TIM9, 1) |
| | TIM9_CH2N on PB1.
|
| #define | TIM9_CH2N_PD10_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 10, TIM9, 2) |
| | TIM9_CH2N on PD10.
|
| #define | TIM9_CH3N_PC2_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 2, TIM9, 0) |
| | TIM9_CH3N on PC2.
|
| #define | TIM9_CH3N_PB2_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 2, TIM9, 1) |
| | TIM9_CH3N on PB2.
|
| #define | TIM9_CH3N_PD12_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, TIM9, 2) |
| | TIM9_CH3N on PD12.
|
| #define | TIM10_ETR_PC10_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 10, TIM10, 0) |
| | TIM10_ETR on PC10.
|
| #define | TIM10_ETR_PB11_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, TIM10, 1) |
| | TIM10_ETR on PB11.
|
| #define | TIM10_ETR_PD0_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 0, TIM10, 2) |
| | TIM10_ETR on PD0.
|
| #define | TIM10_CH1_PB8_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, TIM10, 0) |
| | TIM10_CH1 on PB8.
|
| #define | TIM10_CH1_PB3_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, TIM10, 1) |
| | TIM10_CH1 on PB3.
|
| #define | TIM10_CH1_PD1_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 1, TIM10, 2) |
| | TIM10_CH1 on PD1.
|
| #define | TIM10_CH2_PB9_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, TIM10, 0) |
| | TIM10_CH2 on PB9.
|
| #define | TIM10_CH2_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, TIM10, 1) |
| | TIM10_CH2 on PB4.
|
| #define | TIM10_CH2_PD3_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 3, TIM10, 2) |
| | TIM10_CH2 on PD3.
|
| #define | TIM10_CH3_PC3_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 3, TIM10, 0) |
| | TIM10_CH3 on PC3.
|
| #define | TIM10_CH3_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, TIM10, 1) |
| | TIM10_CH3 on PB5.
|
| #define | TIM10_CH3_PD5_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 5, TIM10, 2) |
| | TIM10_CH3 on PD5.
|
| #define | TIM10_CH4_PC11_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 11, TIM10, 0) |
| | TIM10_CH4 on PC11.
|
| #define | TIM10_CH4_PC15_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 15, TIM10, 1) |
| | TIM10_CH4 on PC15.
|
| #define | TIM10_CH4_PD7_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 7, TIM10, 2) |
| | TIM10_CH4 on PD7.
|
| #define | TIM10_BKIN_PC12_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, TIM10, 0) |
| | TIM10_BKIN on PC12.
|
| #define | TIM10_BKIN_PB10_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, TIM10, 1) |
| | TIM10_BKIN on PB10.
|
| #define | TIM10_BKIN_PE2_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 2, TIM10, 2) |
| | TIM10_BKIN on PE2.
|
| #define | TIM10_CH1N_PA12_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, TIM10, 0) |
| | TIM10_CH1N on PA12.
|
| #define | TIM10_CH1N_PA5_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, TIM10, 1) |
| | TIM10_CH1N on PA5.
|
| #define | TIM10_CH1N_PE3_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 3, TIM10, 2) |
| | TIM10_CH1N on PE3.
|
| #define | TIM10_CH2N_PA13_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 13, TIM10, 0) |
| | TIM10_CH2N on PA13.
|
| #define | TIM10_CH2N_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, TIM10, 1) |
| | TIM10_CH2N on PA6.
|
| #define | TIM10_CH2N_PE4_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 4, TIM10, 2) |
| | TIM10_CH2N on PE4.
|
| #define | TIM10_CH3N_PA14_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, TIM10, 0) |
| | TIM10_CH3N on PA14.
|
| #define | TIM10_CH3N_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, TIM10, 1) |
| | TIM10_CH3N on PA7.
|
| #define | TIM10_CH3N_PE5_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 5, TIM10, 2) |
| | TIM10_CH3N on PE5.
|
1.16.1