Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
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lib_helpers.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2022 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Armv8-R AArch32 architecture helpers.
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*
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_LIB_HELPERS_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_LIB_HELPERS_H_
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#ifndef _ASMLANGUAGE
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#include <
stdint.h
>
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#define read_sysreg32(op1, CRn, CRm, op2) \
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({ \
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uint32_t val; \
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__asm__ volatile ("mrc p15, " #op1 ", %0, c" #CRn ", c" \
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#CRm ", " #op2 : "=r" (val) :: "memory"); \
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val; \
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})
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#define write_sysreg32(val, op1, CRn, CRm, op2) \
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({ \
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__asm__ volatile ("mcr p15, " #op1 ", %0, c" #CRn ", c" \
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#CRm ", " #op2 :: "r" (val) : "memory"); \
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})
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#define read_sysreg64(op1, CRm) \
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({ \
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uint64_t val; \
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__asm__ volatile ("mrrc p15, " #op1 ", %Q0, %R0, c" \
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#CRm : "=r" (val) :: "memory"); \
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val; \
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})
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#define write_sysreg64(val, op1, CRm) \
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({ \
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__asm__ volatile ("mcrr p15, " #op1 ", %Q0, %R0, c" \
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#CRm :: "r" (val) : "memory"); \
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})
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#define MAKE_REG_HELPER(reg, op1, CRn, CRm, op2) \
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static ALWAYS_INLINE uint32_t read_##reg(void) \
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{ \
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return read_sysreg32(op1, CRn, CRm, op2); \
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} \
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static ALWAYS_INLINE void write_##reg(uint32_t val) \
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{ \
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write_sysreg32(val, op1, CRn, CRm, op2); \
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}
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#define MAKE_REG64_HELPER(reg, op1, CRm) \
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static ALWAYS_INLINE uint64_t read_##reg(void) \
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{ \
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return read_sysreg64(op1, CRm); \
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} \
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static ALWAYS_INLINE void write_##reg(uint64_t val) \
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{ \
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write_sysreg64(val, op1, CRm); \
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}
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MAKE_REG_HELPER
(mpuir, 0, 0, 0, 4);
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MAKE_REG_HELPER
(mpidr, 0, 0, 0, 5);
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MAKE_REG_HELPER
(sctlr, 0, 1, 0, 0);
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MAKE_REG_HELPER
(prselr, 0, 6, 2, 1);
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MAKE_REG_HELPER
(prbar, 0, 6, 3, 0);
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MAKE_REG_HELPER
(prlar, 0, 6, 3, 1);
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MAKE_REG_HELPER
(mair0, 0, 10, 2, 0);
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MAKE_REG_HELPER
(vbar, 0, 12, 0, 0);
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MAKE_REG_HELPER
(cntv_ctl, 0, 14, 3, 1);
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MAKE_REG_HELPER
(ctr, 0, 0, 0, 1);
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MAKE_REG_HELPER
(tpidruro, 0, 13, 0, 3);
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MAKE_REG64_HELPER
(
ICC_SGI1R
, 0, 12);
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MAKE_REG64_HELPER
(cntvct, 1, 14);
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MAKE_REG64_HELPER
(cntv_cval, 3, 14);
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/*
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* GIC v3 compatibility macros:
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* ARMv8 AArch32 profile has no mention of
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* ELx in the register names.
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* We define them anyway to reuse the GICv3 driver
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* made for AArch64.
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*/
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/* ICC_PMR */
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MAKE_REG_HELPER
(
ICC_PMR_EL1
, 0, 4, 6, 0);
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/* ICC_IAR1 */
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MAKE_REG_HELPER
(
ICC_IAR1_EL1
, 0, 12, 12, 0);
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/* ICC_EOIR1 */
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MAKE_REG_HELPER
(
ICC_EOIR1_EL1
, 0, 12, 12, 1);
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/* ICC_SRE */
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MAKE_REG_HELPER
(
ICC_SRE_EL1
, 0, 12, 12, 5);
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/* ICC_IGRPEN1 */
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MAKE_REG_HELPER
(
ICC_IGRPEN1_EL1
, 0, 12, 12, 7);
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#define write_sysreg(val, reg) write_##reg(val)
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#define read_sysreg(reg) read_##reg()
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#define sev() __asm__ volatile("sev" : : : "memory")
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#define wfe() __asm__ volatile("wfe" : : : "memory")
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#endif
/* !_ASMLANGUAGE */
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#endif
/* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_LIB_HELPERS_H_ */
ICC_SRE_EL1
#define ICC_SRE_EL1
Definition
cpu.h:146
ICC_IAR1_EL1
#define ICC_IAR1_EL1
Definition
cpu.h:158
ICC_PMR_EL1
#define ICC_PMR_EL1
Definition
cpu.h:151
ICC_EOIR1_EL1
#define ICC_EOIR1_EL1
Definition
cpu.h:160
ICC_SGI1R
#define ICC_SGI1R
Definition
cpu.h:145
ICC_IGRPEN1_EL1
#define ICC_IGRPEN1_EL1
Definition
cpu.h:144
MAKE_REG_HELPER
#define MAKE_REG_HELPER(reg, op1, CRn, CRm, op2)
Definition
lib_helpers.h:45
MAKE_REG64_HELPER
#define MAKE_REG64_HELPER(reg, op1, CRm)
Definition
lib_helpers.h:55
stdint.h
zephyr
arch
arm
cortex_a_r
lib_helpers.h
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