Zephyr API Documentation 3.7.99
A Scalable Open Source RTOS
|
Functions | |
static ALWAYS_INLINE void | barrier_dmem_fence_full (void) |
Full/sequentially-consistent data memory barrier. | |
static ALWAYS_INLINE void | barrier_dsync_fence_full (void) |
Full/sequentially-consistent data synchronization barrier. | |
static ALWAYS_INLINE void | barrier_isync_fence_full (void) |
Full/sequentially-consistent instruction synchronization barrier. | |
|
static |
#include <zephyr/sys/barrier.h>
Full/sequentially-consistent data memory barrier.
This routine acts as a synchronization fence between threads and prevents re-ordering of data accesses instructions across the barrier instruction.
|
static |
#include <zephyr/sys/barrier.h>
Full/sequentially-consistent data synchronization barrier.
This routine acts as a synchronization fence between threads and prevents re-ordering of data accesses instructions across the barrier instruction like barrier_dmem_fence_full(), but has the additional effect of blocking execution of any further instructions, not just loads or stores, or both, until synchronization is complete.
|
static |
#include <zephyr/sys/barrier.h>
Full/sequentially-consistent instruction synchronization barrier.
This routine is used to guarantee that any subsequent instructions are fetched and to ensure any previously executed context-changing operations, such as writes to system control registers, have completed by the time the routine completes. In hardware terms, this might mean that the instruction pipeline is flushed, for example.