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Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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Topics | |
| Renesas RA BSP Clock Clkout Divider Constants | |
| PCLK clock source. | |
| Renesas RA BSP Clock Source Constants | |
| Renesas RA BSP clock source constants. | |
| Renesas RA Clock Divider Generators | |
| Divider generator macros for multiple clock domains. | |
Files | |
| file | renesas_ra_cgc.h |
| Renesas RA Clock Generator Circuit (CGC) header file. | |
Data Structures | |
| struct | clock_control_ra_pclk_cfg |
| Peripheral clock configuration. More... | |
| struct | clock_control_ra_subsys_cfg |
| Subsystem clock control configuration. More... | |
Macros | |
| #define | RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) |
| Conditional property getter based on devicetree status. | |
| #define | RA_CGC_CLK_SRC(node_id) |
| Helper to get clock source form device tree. | |
| #define | RA_CGC_CLK_DIV(clk, prop, default_value) |
| Helper to compute a clock divider. | |
| #define RA_CGC_CLK_DIV | ( | clk, | |
| prop, | |||
| default_value ) |
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
Helper to compute a clock divider.
This macro expands to a RA_CGC_DIV_* prefix combined with a devicetree value.
| #define RA_CGC_CLK_SRC | ( | node_id | ) |
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
Helper to get clock source form device tree.
Expands to a BSP_CLOCKS_SOURCE_* constant when the node is enabled, or BSP_CLOCKS_CLOCK_DISABLED otherwise.
| #define RA_CGC_PROP_HAS_STATUS_OKAY_OR | ( | node_id, | |
| prop, | |||
| default_value ) |
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
Conditional property getter based on devicetree status.
Returns the value of a devicetree property if the node is marked as okay. Otherwise, the provided default value is used.