renesas_ra_cgc.h File Reference

Renesas RA Clock Generator Circuit (CGC) header file. More...

#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>

Go to the source code of this file.

Data Structures
struct	clock_control_ra_pclk_cfg
	Peripheral clock configuration. More...
struct	clock_control_ra_subsys_cfg
	Subsystem clock control configuration. More...

Macros
#define	BSP_CLOCKS_SOURCE_PLL   BSP_CLOCKS_SOURCE_CLOCK_PLL
	PLL clock source.
#define	BSP_CLOCKS_SOURCE_PLLP   BSP_CLOCKS_SOURCE_CLOCK_PLL
	PLLP clock source.
#define	BSP_CLOCKS_SOURCE_PLLQ   BSP_CLOCKS_SOURCE_CLOCK_PLL1Q
	PLLQ clock source.
#define	BSP_CLOCKS_SOURCE_PLLR   BSP_CLOCKS_SOURCE_CLOCK_PLL1R
	PLLR clock source.
#define	BSP_CLOCKS_SOURCE_PLL2   BSP_CLOCKS_SOURCE_CLOCK_PLL2
	PLL2 clock source.
#define	BSP_CLOCKS_SOURCE_PLL2P   BSP_CLOCKS_SOURCE_CLOCK_PLL2
	PLL2P clock source.
#define	BSP_CLOCKS_SOURCE_PLL2Q   BSP_CLOCKS_SOURCE_CLOCK_PLL2Q
	PLL2Q clock source.
#define	BSP_CLOCKS_SOURCE_PLL2R   BSP_CLOCKS_SOURCE_CLOCK_PLL2R
	PLL2R clock source.
#define	BSP_CLOCKS_CLKOUT_DIV_1   (0)
	Clkout div 1.
#define	BSP_CLOCKS_CLKOUT_DIV_2   (1)
	Clkout div 2.
#define	BSP_CLOCKS_CLKOUT_DIV_4   (2)
	Clkout div 4.
#define	BSP_CLOCKS_CLKOUT_DIV_8   (3)
	Clkout div 8.
#define	BSP_CLOCKS_CLKOUT_DIV_16   (4)
	Clkout div 16.
#define	BSP_CLOCKS_CLKOUT_DIV_32   (5)
	Clkout div 32.
#define	BSP_CLOCKS_CLKOUT_DIV_64   (6)
	Clkout div 64.
#define	BSP_CLOCKS_CLKOUT_DIV_128   (7)
	Clkout div 128.
Clock source and divider helpers for Renesas RA devices.
#define	RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value)
	Conditional property getter based on devicetree status.
#define	RA_CGC_CLK_SRC(node_id)
	Helper to get clock source form device tree.
#define	RA_CGC_CLK_DIV(clk, prop, default_value)
	Helper to compute a clock divider.
#define	RA_CGC_DIV_BCLK(n)
	BCLK divider.
#define	RA_CGC_DIV_CANFDCLK(n)
	CANFD divider.
#define	RA_CGC_DIV_CECCLK(n)
	CEC divider.
#define	RA_CGC_DIV_CLKOUT(n)
	CLKOUT divider.
#define	RA_CGC_DIV_CPUCLK0(n)
	CPUCLK0 divider.
#define	RA_CGC_DIV_CPUCLK1(n)
	CPUCLK1 divider.
#define	RA_CGC_DIV_MRPCLK(n)
	MRPCLK divider.
#define	RA_CGC_DIV_CPUCLK(n)
	CPUCLK divider.
#define	RA_CGC_DIV_FCLK(n)
	FCLK divider.
#define	RA_CGC_DIV_I3CCLK(n)
	I3C divider.
#define	RA_CGC_DIV_ICLK(n)
	ICLK divider.
#define	RA_CGC_DIV_LCDCLK(n)
	LCDCLK divider.
#define	RA_CGC_DIV_OCTASPICLK(n)
	OCTASPI divider.
#define	RA_CGC_DIV_PCLKA(n)
	PCLKA divider.
#define	RA_CGC_DIV_PCLKB(n)
	PCLKB divider.
#define	RA_CGC_DIV_PCLKC(n)
	PCLKC divider.
#define	RA_CGC_DIV_PCLKD(n)
	PCLKD divider.
#define	RA_CGC_DIV_PCLKE(n)
	PCLKE divider.
#define	RA_CGC_DIV_PLL(n)
	PLL divider.
#define	RA_CGC_DIV_PLLP(n)
	PLLP divider.
#define	RA_CGC_DIV_PLLQ(n)
	PLLQ divider.
#define	RA_CGC_DIV_PLLR(n)
	PLLR divider.
#define	RA_CGC_DIV_PLL2(n)
	PLL2 divider.
#define	RA_CGC_DIV_PLL2P(n)
	PLL2P divider.
#define	RA_CGC_DIV_PLL2Q(n)
	PLL2Q divider.
#define	RA_CGC_DIV_PLL2R(n)
	PLL2R divider.
#define	RA_CGC_DIV_SCICLK(n)
	SCICLK divider.
#define	RA_CGC_DIV_SPICLK(n)
	SPICLK divider.
#define	RA_CGC_DIV_U60CLK(n)
	U60CLK divider.
#define	RA_CGC_DIV_UCLK(n)
	UCLK divider.
#define	RA_CGC_DIV_SCISPICLK(n)
	SCISPI divider.
#define	RA_CGC_DIV_GPTCLK(n)
	GPTCLK divider.
#define	RA_CGC_DIV_IICCLK(n)
	IICCLK divider.
#define	RA_CGC_DIV_ADCCLK(n)
	ADCCLK divider.
#define	RA_CGC_DIV_MRICLK(n)
	MRICLK divider.
#define	RA_CGC_DIV_NPUCLK(n)
	NPUCLK divider.
#define	RA_CGC_DIV_BCLKA(n)
	BCLKA divider.
#define	RA_CGC_DIV_ESWCLK(n)
	ESWCLK divider.
#define	RA_CGC_DIV_ESWPHYCLK(n)
	ESWPHYCLK divider.
#define	RA_CGC_DIV_ETHPHYCLK(n)
	ETHPHY divider.
#define	RA_CGC_DIV_ESCCLK(n)
	ESCCLK divider.
#define	RA_CGC_DIV_DSMIFCLK(n)
	DSMIFCLK divider.

Detailed Description

Renesas RA Clock Generator Circuit (CGC) header file.

Macro Definition Documentation

RA_CGC_CLK_DIV

#define RA_CGC_CLK_DIV	(		clk,
			prop,
			default_value )

Value:

        UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk))                                  \
        (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value))

Helper to compute a clock divider.

This macro expands to a RA_CGC_DIV_* prefix combined with a devicetree value.

RA_CGC_CLK_SRC

#define RA_CGC_CLK_SRC

(

node_id

)

Value:

        COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \
                (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \
                (BSP_CLOCKS_CLOCK_DISABLED))

Helper to get clock source form device tree.

Expands to a BSP_CLOCKS_SOURCE_* constant when the node is enabled, or BSP_CLOCKS_CLOCK_DISABLED otherwise.

RA_CGC_PROP_HAS_STATUS_OKAY_OR

#define RA_CGC_PROP_HAS_STATUS_OKAY_OR	(		node_id,
			prop,
			default_value )

Value:

        COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \
                (DT_PROP(node_id, prop)), (default_value))

Conditional property getter based on devicetree status.

Returns the value of a devicetree property if the node is marked as okay. Otherwise, the provided default value is used.