Renesas RZ/G pin control helpers

Macros for pin control configuration of Renesas RZ/G SoCs. More...

Files
file	pinctrl-rzg-common.h
	Devicetree pin control helpers for Renesas RZ/G (RZ/G3S).
file	pinctrl-rzg2-common.h
	Renesas RZ/G2L, RZ/G2LC and RZ/G2UL pin and function definitions.
file	pinctrl-rzg3e.h
	Renesas RZ/G3E pin and function definitions.

Macros
#define	RZG_PINMUX(port, pin, func)
	Create an encoded value containing port/pin/function information.
#define	RZG_FILTER_SET(filnum, filclksel)
	Encode filter stage count and clock selection into one configuration value.

Renesas RZ/G digital noise filter options
Set the number of filter stages (FILNUM) and the sampling clock divider (FILCLKSEL).
#define	RZG_FILNUM_4_STAGE   0
	FILNUM: 4-stage filter.
#define	RZG_FILNUM_8_STAGE   1
	FILNUM: 8-stage filter.
#define	RZG_FILNUM_12_STAGE   2
	FILNUM: 12-stage filter.
#define	RZG_FILNUM_16_STAGE   3
	FILNUM: 16-stage filter.
#define	RZG_FILCLKSEL_NOT_DIV   0
	FILCLKSEL: no division.
#define	RZG_FILCLKSEL_DIV_9000   1
	FILCLKSEL: divided by 9000.
#define	RZG_FILCLKSEL_DIV_18000   2
	FILCLKSEL: divided by 18000.
#define	RZG_FILCLKSEL_DIV_36000   3
	FILCLKSEL: divided by 36000.

Detailed Description

Macros for pin control configuration of Renesas RZ/G SoCs.

General-purpose pins are configured with the RZG_PINMUX() macro, which takes three fields:

• port — the port identifier, one of the PORT_* values.
• pin — the pin number within that port.
• func — the alternate-function number selecting the peripheral signal routed to the pin, taken from the SoC's Pin Function Controller table; it has no symbolic macro and is passed as a plain integer.

Dedicated-function pins that sit outside the general-purpose port matrix are referenced directly through their BSP_IO_* identifiers, covering debug (BSP_IO_NMI, BSP_IO_TMS_SWDIO, BSP_IO_TDO), audio clocks, XSPI flash, I3C, SD/MMC and watchdog overflow.

An optional digital noise filter can be applied to a pin group with RZG_FILTER_SET(), built from a stage count (RZG_FILNUM_*) and a sampling clock divider (RZG_FILCLKSEL_*).

The pre-defined port/pin combinations differ between RZ/G variants and are provided by a dedicated header per variant:

• pinctrl-rzg-common.h — RZ/G3S
• pinctrl-rzg2-common.h — RZ/G2L, RZ/G2LC, RZ/G2UL
• pinctrl-rzg3e.h — RZ/G3E

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>
 
&pinctrl {
        scif0_default: scif0_default {
                device-pinmux {
                        pinmux = <RZG_PINMUX(PORT_08, 1, 5)>,
                                 <RZG_PINMUX(PORT_08, 2, 5)>;
                        bias-pull-up;
                        renesas,filter =
                                RZG_FILTER_SET(RZG_FILNUM_8_STAGE, RZG_FILCLKSEL_DIV_18000);
                };
        };
};

Macro Definition Documentation

RZG_FILCLKSEL_DIV_18000

#define RZG_FILCLKSEL_DIV_18000   2

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILCLKSEL: divided by 18000.

RZG_FILCLKSEL_DIV_36000

#define RZG_FILCLKSEL_DIV_36000   3

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILCLKSEL: divided by 36000.

RZG_FILCLKSEL_DIV_9000

#define RZG_FILCLKSEL_DIV_9000   1

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILCLKSEL: divided by 9000.

RZG_FILCLKSEL_NOT_DIV

#define RZG_FILCLKSEL_NOT_DIV   0

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILCLKSEL: no division.

RZG_FILNUM_12_STAGE

#define RZG_FILNUM_12_STAGE   2

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILNUM: 12-stage filter.

RZG_FILNUM_16_STAGE

#define RZG_FILNUM_16_STAGE   3

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILNUM: 16-stage filter.

RZG_FILNUM_4_STAGE

#define RZG_FILNUM_4_STAGE   0

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILNUM: 4-stage filter.

RZG_FILNUM_8_STAGE

#define RZG_FILNUM_8_STAGE   1

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

FILNUM: 8-stage filter.

RZG_FILTER_SET

#define RZG_FILTER_SET	(		filnum,
			filclksel )

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

Value:

(((filnum) & 0x3) << 0x2) | (filclksel & 0x3)

Encode filter stage count and clock selection into one configuration value.

Encoding:

• bits [3:2] = FILNUM (masked to 2 bits)
• bits [1:0] = FILCLKSEL (masked to 2 bits)

Parameters

filnum	Filter stage selection (RZG_FILNUM_*).
filclksel	Filter clock selection (RZG_FILCLKSEL_*).

Returns

Encoded filter configuration value.

RZG_PINMUX

#define RZG_PINMUX	(		port,
			pin,
			func )

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h>

Value:

(port | pin | (func << 4))

Create an encoded value containing port/pin/function information.

Parameters

port	Port identifier (PORT_00..PORT_18).
pin	Pin number within the port.
func	Pin function selector.

Returns

Encoded pinmux value.