Silicon Labs xG24 pin control helpers

Macros for pin control configuration of Silicon Labs xG24. More...

Files
file	xg24-pinctrl.h
	Devicetree pin control helpers for Silicon Labs xG24.

Detailed Description

Macros for pin control configuration of Silicon Labs xG24.

The macros follow the following naming convention: <PERIPHERAL>_<SIGNAL>_P<PORT>_<PIN>.

For example, USART0_TX_PC0 corresponds to the TX signal of USART0 mapped to routing port C pin 0.

#include <zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
 
&pinctrl {
        usart0_default: usart0_default {
                group0 {
                        pins = <USART0_TX_PC0>, <USART0_CLK_PC2>;
                        drive-push-pull;
                        output-high;
                };
                group1 {
                        pins = <USART0_RX_PC1>;
                        input-enable;
                };
        };
};

Valid peripherals and signals are:

• ACMP0: ACMPOUT
• ACMP1: ACMPOUT
• CMU: CLKIN0, CLKOUT0, CLKOUT1, CLKOUT2
• EUSART0: CS, CTS, RTS, RX, SCLK, TX
• EUSART1: CS, CTS, RTS, RX, SCLK, TX
• GPIO: SWCLKTCK, SWDIOTMS, SWV, TDI, TDO, TRACECLK, TRACEDATA0, TRACEDATA1, TRACEDATA2, TRACEDATA3
• HFXO0: BUFOUTREQINASYNC
• I2C0: SCL, SDA
• I2C1: SCL, SDA
• KEYSCAN: COLOUT0, COLOUT1, COLOUT2, COLOUT3, COLOUT4, COLOUT5, COLOUT6, COLOUT7, ROWSENSE0, ROWSENSE1, ROWSENSE2, ROWSENSE3, ROWSENSE4, ROWSENSE5
• LETIMER0: OUT0, OUT1
• MODEM: ANT0, ANT1, ANTROLLOVER, ANTRR0, ANTRR1, ANTRR2, ANTRR3, ANTRR4, ANTRR5, ANTSWEN, ANTSWUS, ANTTRIG, ANTTRIGSTOP, DCLK, DIN, DOUT
• PCNT0: S0IN, S1IN
• PRS0: ASYNCH0, ASYNCH1, ASYNCH10, ASYNCH11, ASYNCH12, ASYNCH13, ASYNCH14, ASYNCH15, ASYNCH2, ASYNCH3, ASYNCH4, ASYNCH5, ASYNCH6, ASYNCH7, ASYNCH8, ASYNCH9, SYNCH0, SYNCH1, SYNCH2, SYNCH3
• PTI: DCLK, DFRAME, DOUT
• RAC: LNAEN, PAEN
• TIMER0: CC0, CC1, CC2, CDTI0, CDTI1, CDTI2
• TIMER1: CC0, CC1, CC2, CDTI0, CDTI1, CDTI2
• TIMER2: CC0, CC1, CC2, CDTI0, CDTI1, CDTI2
• TIMER3: CC0, CC1, CC2, CDTI0, CDTI1, CDTI2
• TIMER4: CC0, CC1, CC2, CDTI0, CDTI1, CDTI2
• USART0: CLK, CS, CTS, RTS, RX, TX