mchp_clock_pic32cm_pl.h

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/*
 * Copyright (c) 2026 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CM_PL_H_
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CM_PL_H_
 
#include <zephyr/dt-bindings/clock/mchp_pic32cm_pl_clock.h>


struct clock_mchp_subsys_oschf_config {
        bool on_demand_en;
};

enum clock_mchp_freq {
        CLOCK_FREQ_1KHZ = 1024,
        CLOCK_FREQ_32KHZ = 32768,
        CLOCK_FREQ_1MHZ = 1000000,
        CLOCK_FREQ_2MHZ = 2000000,
        CLOCK_FREQ_3MHZ = 3000000,
        CLOCK_FREQ_4MHZ = 4000000,
        CLOCK_FREQ_8MHZ = 8000000,
        CLOCK_FREQ_12MHZ = 12000000,
        CLOCK_FREQ_20MHZ = 20000000,
        CLOCK_FREQ_24MHZ = 24000000,
};

enum clock_mchp_gclk_src_clock {
        CLOCK_MCHP_GCLK_SRC_OSCHF = 0,
        CLOCK_MCHP_GCLK_SRC_OSC32K,
        CLOCK_MCHP_GCLK_SRC_XOSC32K,
        CLOCK_MCHP_GCLK_SRC_GCLKPIN,
        CLOCK_MCHP_GCLK_SRC_GCLKGEN1,
        CLOCK_MCHP_GCLK_SRC_COUNT
};

enum clock_mchp_gclkgen {
        CLOCK_MCHP_GCLKGEN_GEN0,
        CLOCK_MCHP_GCLKGEN_GEN1,
        CLOCK_MCHP_GCLKGEN_GEN2,
        CLOCK_MCHP_GCLKGEN_GEN3,
        CLOCK_MCHP_GCLKGEN_MAX
};

typedef uint32_t *clock_mchp_rate_t;

 
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MCHP_CLOCK_PIC32CM_PL_H_ */