mchp_pic32cm_pl_clock.h File Reference

List clock subsystem IDs for pic32cm_jh family. More...

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Macros
#define	SUBSYS_TYPE_OSCHF   (0)
	Subsystem type: On-chip oscillator high frequency (OSCHF).
#define	SUBSYS_TYPE_RTC   (1)
	Subsystem type: Real-Time Counter (RTC).
#define	SUBSYS_TYPE_XOSC32K   (2)
	Subsystem type: External 32 kHz crystal oscillator (XOSC32K).
#define	SUBSYS_TYPE_OSC32K   (3)
	Subsystem type: Internal 32 kHz oscillator (OSC32K).
#define	SUBSYS_TYPE_GCLKGEN   (4)
	Subsystem type: Generic Clock Generator (GCLK GEN).
#define	SUBSYS_TYPE_GCLKPERIPH   (5)
	Subsystem type: Generic Clock Peripheral Channel (GCLK PERIPH).
#define	SUBSYS_TYPE_MCLKCPU   (6)
	Subsystem type: Main Clock - CPU domain (MCLK CPU).
#define	SUBSYS_TYPE_MCLKPERIPH   (7)
	Subsystem type: Main Clock - peripheral domain (MCLK PERIPH).
#define	SUBSYS_TYPE_MAX   (7)
	Maximum valid subsystem type value.
#define	MBUS_AHB   (0)
	Main bus type: Advanced High-performance Bus (AHB).
#define	MBUS_APBA   (1)
	Main bus type: Advanced Peripheral Bus A (APBA).
#define	MBUS_APBB   (2)
	Main bus type: Advanced Peripheral Bus B (APBB).
#define	MBUS_APBC   (3)
	Main bus type: Advanced Peripheral Bus C (APBC).
#define	MBUS_MAX   (3)
	Maximum value of Main Bus types.
#define	INST_XOSC32K_XOSC1K   0
	XOSC32K instance: 1 kHz crystal oscillator (XOSC1K).
#define	INST_XOSC32K_XOSC32K   1
	XOSC32K instance: 32.768 kHz crystal oscillator (XOSC32K).
#define	INST_OSC32K_OSC1K   0
	OSC32K instance: 1 kHz internal oscillator (OSC1K).
#define	INST_OSC32K_OSC32K   1
	OSC32K instance: 32.768 kHz internal oscillator (OSC32K).
#define	MCHP_CLOCK_DERIVE_ID(type, mclkbus, mclkmaskbit, gclkperiph, inst)
	Encode clock type, MCLK bus, MCLK mask bit, GCLK PCH and instance number.
#define	CLOCK_MCHP_OSCHF_ID   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_OSCHF, 0x3f, 0x3f, 0x3f, 0)
	Clock ID for the OSCHF subsystem (no MCLK/GCLK dependency fields; set to 0x3f).
#define	CLOCK_MCHP_OSCHF_ID_MAX   (0)
	Maximum OSCHF clock instance ID (highest valid OSCHF instance index).
#define	CLOCK_MCHP_RTC_ID   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_RTC, 0x3f, 0x3f, 0x3f, 0)
	Clock ID for the RTC subsystem (no MCLK/GCLK dependency fields; set to 0x3f).
#define	CLOCK_MCHP_RTC_ID_MAX   (0)
	Maximum RTC clock instance ID (highest valid RTC instance index).
#define	CLOCK_MCHP_XOSC32K_ID_XOSC1K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_XOSC32K, 0x3f, 0x3f, 0x3f, INST_XOSC32K_XOSC1K)
	Clock ID for XOSC32K instance XOSC1K (no MCLK/GCLK dependency fields; set to 0x3f).
#define	CLOCK_MCHP_XOSC32K_ID_XOSC32K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_XOSC32K, 0x3f, 0x3f, 0x3f, INST_XOSC32K_XOSC32K)
	Clock ID for XOSC32K instance XOSC32K (no MCLK/GCLK dependency fields; set to 0x3f).
#define	CLOCK_MCHP_XOSC32K_ID_MAX   (1)
	Maximum XOSC32K clock instance ID (highest valid XOSC32K instance index).
#define	CLOCK_MCHP_OSC32K_ID_OSC1K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_OSC32K, 0x3f, 0x3f, 0x3f, INST_OSC32K_OSC1K)
	Clock ID for OSC32K instance OSC1K (no MCLK/GCLK dependency fields; set to 0x3f).
#define	CLOCK_MCHP_OSC32K_ID_OSC32K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_OSC32K, 0x3f, 0x3f, 0x3f, INST_OSC32K_OSC32K)
	Clock ID for OSC32K instance OSC32K (no MCLK/GCLK dependency fields; set to 0x3f).
#define	CLOCK_MCHP_OSC32K_ID_MAX   (1)
	Maximum OSC32K clock instance ID (highest valid OSC32K instance index).
#define	CLOCK_MCHP_GCLKGEN_ID_GEN0   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 0)
	Clock ID for Generic Clock Generator 0 (GEN0).
#define	CLOCK_MCHP_GCLKGEN_ID_GEN1   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 1)
	Clock ID for Generic Clock Generator 1 (GEN1).
#define	CLOCK_MCHP_GCLKGEN_ID_GEN2   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 2)
	Clock ID for Generic Clock Generator 2 (GEN2).
#define	CLOCK_MCHP_GCLKGEN_ID_GEN3   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 3)
	Clock ID for Generic Clock Generator 3 (GEN3).
#define	CLOCK_MCHP_GCLKGEN_ID_MAX   (3)
	Maximum GCLK generator clock instance ID (highest valid generator index).
#define	GCLK_IO_MAX   CLOCK_MCHP_GCLKGEN_ID_MAX
	Maximum GCLK I/O generator index.
#define	CLOCK_MCHP_GCLKPERIPH_ID_EIC   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 0, 0)
	GCLK peripheral clock ID for EIC (PCHCTRL0).
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 1, 1)
	GCLK peripheral clock ID for EVSYS channel 0 (PCHCTRL1).
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 2, 2)
	GCLK peripheral clock ID for EVSYS channel 1 (PCHCTRL2).
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_2    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 3, 3)
	GCLK peripheral clock ID for EVSYS channel 2 (PCHCTRL3).
#define	CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_3    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 4, 4)
	GCLK peripheral clock ID for EVSYS channel 3 (PCHCTRL4).
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_SLOW    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 5, 5)
	GCLK peripheral clock ID for SERCOM0 slow clock (PCHCTRL5).
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_CORE    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 6, 6)
	GCLK peripheral clock ID for SERCOM0 core clock (PCHCTRL6).
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_SLOW    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 7, 7)
	GCLK peripheral clock ID for SERCOM1 slow clock (PCHCTRL7).
#define	CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_CORE    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 8, 8)
	GCLK peripheral clock ID for SERCOM1 core clock (PCHCTRL8).
#define	CLOCK_MCHP_GCLKPERIPH_ID_TC0_TC1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 9, 9)
	GCLK peripheral clock ID for TC0/TC1 (PCHCTRL9).
#define	CLOCK_MCHP_GCLKPERIPH_ID_TC2    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 10, 10)
	GCLK peripheral clock ID for TC2 (PCHCTRL10).
#define	CLOCK_MCHP_GCLKPERIPH_ID_TCC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 11, 11)
	GCLK peripheral clock ID for TCC0 (PCHCTRL11).
#define	CLOCK_MCHP_GCLKPERIPH_ID_CCL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 12, 12)
	GCLK peripheral clock ID for CCL (PCHCTRL12).
#define	CLOCK_MCHP_GCLKPERIPH_ID_MAX   (12)
	Maximum GCLK peripheral clock channel index (highest valid PCHCTRLm index).
#define	GCLK_PH_MAX   CLOCK_MCHP_GCLKPERIPH_ID_MAX
	Maximum GCLK peripheral channel index.
#define	CLOCK_MCHP_MCLKCPU_ID   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKCPU, 0x3f, 0x3f, 0x3f, 0)
	Clock ID for the CPU MCLK domain (no bus/mask/GCLK fields; set to 0x3f).
#define	CLOCK_MCHP_MCLKCPU_MAX   (0)
	Maximum CPU MCLK clock instance ID (highest valid CPU-domain instance index).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBA    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 0, 0x3f, 0)
	MCLK peripheral clock ID for the AHB->APBA bridge (mask bit 0).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBB    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 1, 0x3f, 1)
	MCLK peripheral clock ID for the AHB->APBB bridge (mask bit 1).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 2, 0x3f, 2)
	MCLK peripheral clock ID for the AHB->APBC bridge (mask bit 2).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_DSU    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 3, 0x3f, 3)
	MCLK peripheral clock ID for DSU on AHB (mask bit 3).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_HMATRIXHS    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 4, 0x3f, 4)
	MCLK peripheral clock ID for HMATRIXHS on AHB (mask bit 4).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_NVMCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 5, 0x3f, 5)
	MCLK peripheral clock ID for NVMCTRL on AHB (mask bit 5).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_HSRAM    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 6, 0x3f, 6)
	MCLK peripheral clock ID for HSRAM on AHB (mask bit 6).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_DMAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 7, 0x3f, 7)
	MCLK peripheral clock ID for DMAC on AHB (mask bit 7).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_PAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 8, 0x3f, 8)
	MCLK peripheral clock ID for PAC on AHB (mask bit 8).
#define	CLOCK_MCHP_MCLKPERIPH_ID_AHB_BROM    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 9, 0x3f, 9)
	MCLK peripheral clock ID for BROM on AHB (mask bit 9).
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_PAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 0, 0x3f, 10)
	MCLKPERIPH derive ID for PAC on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_PM    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 1, 0x3f, 11)
	MCLKPERIPH derive ID for PM on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_MCLK    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 2, 0x3f, 12)
	MCLKPERIPH derive ID for MCLK on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_RSTC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 3, 0x3f, 13)
	MCLKPERIPH derive ID for RSTC on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_OSCCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 4, 0x3f, 14)
	MCLKPERIPH derive ID for OSCCTRL on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_OSC32KCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 5, 0x3f, 15)
	MCLKPERIPH derive ID for OSC32KCTRL on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_SUPC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 6, 0x3f, 16)
	MCLKPERIPH derive ID for SUPC on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_GCLK    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 7, 0x3f, 17)
	MCLKPERIPH derive ID for GCLK on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_WDT    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 8, 0x3f, 18)
	MCLKPERIPH derive ID for WDT on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_RTC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 9, 0x3f, 19)
	MCLKPERIPH derive ID for RTC on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBA_EIC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 10, 0x3f, 20)
	MCLKPERIPH derive ID for EIC on APBA bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBB_PORT    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 0, 0x3f, 21)
	MCLKPERIPH derive ID for PORT on APBB bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBB_DSU    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 1, 0x3f, 22)
	MCLKPERIPH derive ID for DSU on APBB bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBB_NVMCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 2, 0x3f, 23)
	MCLKPERIPH derive ID for NVMCTRL on APBB bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBB_DMAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 3, 0x3f, 24)
	MCLKPERIPH derive ID for DMAC on APBB bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBB_MTB    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 4, 0x3f, 25)
	MCLKPERIPH derive ID for MTB on APBB bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBB_HMATRIXHS    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 5, 0x3f, 26)
	MCLKPERIPH derive ID for HMATRIXHS on APBB bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_EVSYS    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 0, 0x3f, 27)
	MCLKPERIPH derive ID for EVSYS on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_SERCOM0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 1, 0x3f, 28)
	MCLKPERIPH derive ID for SERCOM0 on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_SERCOM1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 2, 0x3f, 29)
	MCLKPERIPH derive ID for SERCOM1 on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 3, 0x3f, 30)
	MCLKPERIPH derive ID for TC0 on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 4, 0x3f, 31)
	MCLKPERIPH derive ID for TC1 on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC2    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 5, 0x3f, 32)
	MCLKPERIPH derive ID for TC2 on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_TCC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 6, 0x3f, 33)
	MCLKPERIPH derive ID for TCC0 on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_ADC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 7, 0x3f, 34)
	MCLKPERIPH derive ID for ADC0 on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_AC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 8, 0x3f, 35)
	MCLKPERIPH derive ID for AC on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_CCL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 9, 0x3f, 36)
	MCLKPERIPH derive ID for CCL on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_PTC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 10, 0x3f, 37)
	MCLKPERIPH derive ID for PTC on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_APBC_SYSCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 11, 0x3f, 38)
	MCLKPERIPH derive ID for SYSCTRL on APBC bus.
#define	CLOCK_MCHP_MCLKPERIPH_ID_MAX   (38)
	Maximum valid MCLKPERIPH derive ID value.

Detailed Description

List clock subsystem IDs for pic32cm_jh family.

Clock subsystem IDs. To be used in devicetree nodes, and as argument for clock API.

Macro Definition Documentation

CLOCK_MCHP_GCLKGEN_ID_GEN0

#define CLOCK_MCHP_GCLKGEN_ID_GEN0   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 0)

Clock ID for Generic Clock Generator 0 (GEN0).

CLOCK_MCHP_GCLKGEN_ID_GEN1

#define CLOCK_MCHP_GCLKGEN_ID_GEN1   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 1)

Clock ID for Generic Clock Generator 1 (GEN1).

CLOCK_MCHP_GCLKGEN_ID_GEN2

#define CLOCK_MCHP_GCLKGEN_ID_GEN2   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 2)

Clock ID for Generic Clock Generator 2 (GEN2).

CLOCK_MCHP_GCLKGEN_ID_GEN3

#define CLOCK_MCHP_GCLKGEN_ID_GEN3   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKGEN, 0x3f, 0x3f, 0x3f, 3)

Clock ID for Generic Clock Generator 3 (GEN3).

CLOCK_MCHP_GCLKGEN_ID_MAX

#define CLOCK_MCHP_GCLKGEN_ID_MAX   (3)

Maximum GCLK generator clock instance ID (highest valid generator index).

CLOCK_MCHP_GCLKPERIPH_ID_CCL

#define CLOCK_MCHP_GCLKPERIPH_ID_CCL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 12, 12)

GCLK peripheral clock ID for CCL (PCHCTRL12).

CLOCK_MCHP_GCLKPERIPH_ID_EIC

#define CLOCK_MCHP_GCLKPERIPH_ID_EIC   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 0, 0)

GCLK peripheral clock ID for EIC (PCHCTRL0).

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_0

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 1, 1)

GCLK peripheral clock ID for EVSYS channel 0 (PCHCTRL1).

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_1

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 2, 2)

GCLK peripheral clock ID for EVSYS channel 1 (PCHCTRL2).

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_2

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_2    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 3, 3)

GCLK peripheral clock ID for EVSYS channel 2 (PCHCTRL3).

CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_3

#define CLOCK_MCHP_GCLKPERIPH_ID_EVSYS_CHANNEL_3    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 4, 4)

GCLK peripheral clock ID for EVSYS channel 3 (PCHCTRL4).

CLOCK_MCHP_GCLKPERIPH_ID_MAX

#define CLOCK_MCHP_GCLKPERIPH_ID_MAX   (12)

Maximum GCLK peripheral clock channel index (highest valid PCHCTRLm index).

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_CORE    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 6, 6)

GCLK peripheral clock ID for SERCOM0 core clock (PCHCTRL6).

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_SLOW

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM0_SLOW    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 5, 5)

GCLK peripheral clock ID for SERCOM0 slow clock (PCHCTRL5).

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_CORE

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_CORE    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 8, 8)

GCLK peripheral clock ID for SERCOM1 core clock (PCHCTRL8).

CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_SLOW

#define CLOCK_MCHP_GCLKPERIPH_ID_SERCOM1_SLOW    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 7, 7)

GCLK peripheral clock ID for SERCOM1 slow clock (PCHCTRL7).

CLOCK_MCHP_GCLKPERIPH_ID_TC0_TC1

#define CLOCK_MCHP_GCLKPERIPH_ID_TC0_TC1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 9, 9)

GCLK peripheral clock ID for TC0/TC1 (PCHCTRL9).

CLOCK_MCHP_GCLKPERIPH_ID_TC2

#define CLOCK_MCHP_GCLKPERIPH_ID_TC2    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 10, 10)

GCLK peripheral clock ID for TC2 (PCHCTRL10).

CLOCK_MCHP_GCLKPERIPH_ID_TCC0

#define CLOCK_MCHP_GCLKPERIPH_ID_TCC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 11, 11)

GCLK peripheral clock ID for TCC0 (PCHCTRL11).

CLOCK_MCHP_MCLKCPU_ID

#define CLOCK_MCHP_MCLKCPU_ID   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKCPU, 0x3f, 0x3f, 0x3f, 0)

Clock ID for the CPU MCLK domain (no bus/mask/GCLK fields; set to 0x3f).

CLOCK_MCHP_MCLKCPU_MAX

#define CLOCK_MCHP_MCLKCPU_MAX   (0)

Maximum CPU MCLK clock instance ID (highest valid CPU-domain instance index).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBA

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBA    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 0, 0x3f, 0)

MCLK peripheral clock ID for the AHB->APBA bridge (mask bit 0).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBB

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBB    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 1, 0x3f, 1)

MCLK peripheral clock ID for the AHB->APBB bridge (mask bit 1).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBC

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 2, 0x3f, 2)

MCLK peripheral clock ID for the AHB->APBC bridge (mask bit 2).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_BROM

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_BROM    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 9, 0x3f, 9)

MCLK peripheral clock ID for BROM on AHB (mask bit 9).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_DMAC

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_DMAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 7, 0x3f, 7)

MCLK peripheral clock ID for DMAC on AHB (mask bit 7).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_DSU

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_DSU    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 3, 0x3f, 3)

MCLK peripheral clock ID for DSU on AHB (mask bit 3).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_HMATRIXHS

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_HMATRIXHS    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 4, 0x3f, 4)

MCLK peripheral clock ID for HMATRIXHS on AHB (mask bit 4).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_HSRAM

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_HSRAM    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 6, 0x3f, 6)

MCLK peripheral clock ID for HSRAM on AHB (mask bit 6).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_NVMCTRL

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_NVMCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 5, 0x3f, 5)

MCLK peripheral clock ID for NVMCTRL on AHB (mask bit 5).

CLOCK_MCHP_MCLKPERIPH_ID_AHB_PAC

#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_PAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_AHB, 8, 0x3f, 8)

MCLK peripheral clock ID for PAC on AHB (mask bit 8).

CLOCK_MCHP_MCLKPERIPH_ID_APBA_EIC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_EIC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 10, 0x3f, 20)

MCLKPERIPH derive ID for EIC on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_GCLK

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_GCLK    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 7, 0x3f, 17)

MCLKPERIPH derive ID for GCLK on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_MCLK

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_MCLK    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 2, 0x3f, 12)

MCLKPERIPH derive ID for MCLK on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_OSC32KCTRL

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_OSC32KCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 5, 0x3f, 15)

MCLKPERIPH derive ID for OSC32KCTRL on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_OSCCTRL

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_OSCCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 4, 0x3f, 14)

MCLKPERIPH derive ID for OSCCTRL on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_PAC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_PAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 0, 0x3f, 10)

MCLKPERIPH derive ID for PAC on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_PM

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_PM    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 1, 0x3f, 11)

MCLKPERIPH derive ID for PM on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_RSTC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_RSTC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 3, 0x3f, 13)

MCLKPERIPH derive ID for RSTC on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_RTC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_RTC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 9, 0x3f, 19)

MCLKPERIPH derive ID for RTC on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_SUPC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_SUPC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 6, 0x3f, 16)

MCLKPERIPH derive ID for SUPC on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBA_WDT

#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_WDT    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBA, 8, 0x3f, 18)

MCLKPERIPH derive ID for WDT on APBA bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBB_DMAC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBB_DMAC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 3, 0x3f, 24)

MCLKPERIPH derive ID for DMAC on APBB bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBB_DSU

#define CLOCK_MCHP_MCLKPERIPH_ID_APBB_DSU    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 1, 0x3f, 22)

MCLKPERIPH derive ID for DSU on APBB bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBB_HMATRIXHS

#define CLOCK_MCHP_MCLKPERIPH_ID_APBB_HMATRIXHS    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 5, 0x3f, 26)

MCLKPERIPH derive ID for HMATRIXHS on APBB bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBB_MTB

#define CLOCK_MCHP_MCLKPERIPH_ID_APBB_MTB    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 4, 0x3f, 25)

MCLKPERIPH derive ID for MTB on APBB bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBB_NVMCTRL

#define CLOCK_MCHP_MCLKPERIPH_ID_APBB_NVMCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 2, 0x3f, 23)

MCLKPERIPH derive ID for NVMCTRL on APBB bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBB_PORT

#define CLOCK_MCHP_MCLKPERIPH_ID_APBB_PORT    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBB, 0, 0x3f, 21)

MCLKPERIPH derive ID for PORT on APBB bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_AC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_AC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 8, 0x3f, 35)

MCLKPERIPH derive ID for AC on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_ADC0

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_ADC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 7, 0x3f, 34)

MCLKPERIPH derive ID for ADC0 on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_CCL

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_CCL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 9, 0x3f, 36)

MCLKPERIPH derive ID for CCL on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_EVSYS

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_EVSYS    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 0, 0x3f, 27)

MCLKPERIPH derive ID for EVSYS on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_PTC

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_PTC    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 10, 0x3f, 37)

MCLKPERIPH derive ID for PTC on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_SERCOM0

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_SERCOM0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 1, 0x3f, 28)

MCLKPERIPH derive ID for SERCOM0 on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_SERCOM1

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_SERCOM1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 2, 0x3f, 29)

MCLKPERIPH derive ID for SERCOM1 on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_SYSCTRL

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_SYSCTRL    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 11, 0x3f, 38)

MCLKPERIPH derive ID for SYSCTRL on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC0

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 3, 0x3f, 30)

MCLKPERIPH derive ID for TC0 on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC1

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC1    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 4, 0x3f, 31)

MCLKPERIPH derive ID for TC1 on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC2

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_TC2    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 5, 0x3f, 32)

MCLKPERIPH derive ID for TC2 on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_APBC_TCC0

#define CLOCK_MCHP_MCLKPERIPH_ID_APBC_TCC0    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_MCLKPERIPH, MBUS_APBC, 6, 0x3f, 33)

MCLKPERIPH derive ID for TCC0 on APBC bus.

CLOCK_MCHP_MCLKPERIPH_ID_MAX

#define CLOCK_MCHP_MCLKPERIPH_ID_MAX   (38)

Maximum valid MCLKPERIPH derive ID value.

CLOCK_MCHP_OSC32K_ID_MAX

#define CLOCK_MCHP_OSC32K_ID_MAX   (1)

Maximum OSC32K clock instance ID (highest valid OSC32K instance index).

CLOCK_MCHP_OSC32K_ID_OSC1K

#define CLOCK_MCHP_OSC32K_ID_OSC1K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_OSC32K, 0x3f, 0x3f, 0x3f, INST_OSC32K_OSC1K)

Clock ID for OSC32K instance OSC1K (no MCLK/GCLK dependency fields; set to 0x3f).

CLOCK_MCHP_OSC32K_ID_OSC32K

#define CLOCK_MCHP_OSC32K_ID_OSC32K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_OSC32K, 0x3f, 0x3f, 0x3f, INST_OSC32K_OSC32K)

Clock ID for OSC32K instance OSC32K (no MCLK/GCLK dependency fields; set to 0x3f).

CLOCK_MCHP_OSCHF_ID

#define CLOCK_MCHP_OSCHF_ID   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_OSCHF, 0x3f, 0x3f, 0x3f, 0)

Clock ID for the OSCHF subsystem (no MCLK/GCLK dependency fields; set to 0x3f).

CLOCK_MCHP_OSCHF_ID_MAX

#define CLOCK_MCHP_OSCHF_ID_MAX   (0)

Maximum OSCHF clock instance ID (highest valid OSCHF instance index).

CLOCK_MCHP_RTC_ID

#define CLOCK_MCHP_RTC_ID   MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_RTC, 0x3f, 0x3f, 0x3f, 0)

Clock ID for the RTC subsystem (no MCLK/GCLK dependency fields; set to 0x3f).

CLOCK_MCHP_RTC_ID_MAX

#define CLOCK_MCHP_RTC_ID_MAX   (0)

Maximum RTC clock instance ID (highest valid RTC instance index).

CLOCK_MCHP_XOSC32K_ID_MAX

#define CLOCK_MCHP_XOSC32K_ID_MAX   (1)

Maximum XOSC32K clock instance ID (highest valid XOSC32K instance index).

CLOCK_MCHP_XOSC32K_ID_XOSC1K

#define CLOCK_MCHP_XOSC32K_ID_XOSC1K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_XOSC32K, 0x3f, 0x3f, 0x3f, INST_XOSC32K_XOSC1K)

Clock ID for XOSC32K instance XOSC1K (no MCLK/GCLK dependency fields; set to 0x3f).

CLOCK_MCHP_XOSC32K_ID_XOSC32K

#define CLOCK_MCHP_XOSC32K_ID_XOSC32K    MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_XOSC32K, 0x3f, 0x3f, 0x3f, INST_XOSC32K_XOSC32K)

Clock ID for XOSC32K instance XOSC32K (no MCLK/GCLK dependency fields; set to 0x3f).

GCLK_IO_MAX

#define GCLK_IO_MAX   CLOCK_MCHP_GCLKGEN_ID_MAX

Maximum GCLK I/O generator index.

GCLK_PH_MAX

#define GCLK_PH_MAX   CLOCK_MCHP_GCLKPERIPH_ID_MAX

Maximum GCLK peripheral channel index.

INST_OSC32K_OSC1K

#define INST_OSC32K_OSC1K   0

OSC32K instance: 1 kHz internal oscillator (OSC1K).

INST_OSC32K_OSC32K

#define INST_OSC32K_OSC32K   1

OSC32K instance: 32.768 kHz internal oscillator (OSC32K).

INST_XOSC32K_XOSC1K

#define INST_XOSC32K_XOSC1K   0

XOSC32K instance: 1 kHz crystal oscillator (XOSC1K).

INST_XOSC32K_XOSC32K

#define INST_XOSC32K_XOSC32K   1

XOSC32K instance: 32.768 kHz crystal oscillator (XOSC32K).

MBUS_AHB

#define MBUS_AHB   (0)

Main bus type: Advanced High-performance Bus (AHB).

MBUS_APBA

#define MBUS_APBA   (1)

Main bus type: Advanced Peripheral Bus A (APBA).

MBUS_APBB

#define MBUS_APBB   (2)

Main bus type: Advanced Peripheral Bus B (APBB).

MBUS_APBC

#define MBUS_APBC   (3)

Main bus type: Advanced Peripheral Bus C (APBC).

MBUS_MAX

#define MBUS_MAX   (3)

Maximum value of Main Bus types.

MCHP_CLOCK_DERIVE_ID

#define MCHP_CLOCK_DERIVE_ID	(		type,
			mclkbus,
			mclkmaskbit,
			gclkperiph,
			inst )

Value:

        (((type) << 26) | ((mclkbus) << 20) | ((mclkmaskbit) << 14) | ((gclkperiph) << 8) | inst)

Encode clock type, MCLK bus, MCLK mask bit, GCLK PCH and instance number.

Encodes clock subsystem selection fields into a single packed 32-bit identifier.

Bit fields:

• Bits [7:0] : inst (8 bits)
• Bits [13:8] : gclkperiph (6 bits, valid 0..12)
• Bits [19:14] : mclkmaskbit (6 bits, valid 0..31)
• Bits [25:20] : mclkbus (6 bits), one of:
  • MBUS_AHB (0)
  • MBUS_APBA (1)
  • MBUS_APBB (2)
  • MBUS_APBC (3)
• Bits [31:26] : type (6 bits), one of:
  • SUBSYS_TYPE_OSCHF (0)
  • SUBSYS_TYPE_RTC (1)
  • SUBSYS_TYPE_XOSC32K (2)
  • SUBSYS_TYPE_OSC32K (3)
  • SUBSYS_TYPE_GCLKGEN (4)
  • SUBSYS_TYPE_GCLKPERIPH (5)
  • SUBSYS_TYPE_MCLKCPU (6)
  • SUBSYS_TYPE_MCLKPERIPH (7)

Parameters

type	Clock subsystem type.
mclkbus	Select from the AHBx/APBx buses (see MBUS_*).
mclkmaskbit	Module mask bit on the selected AHBx/APBx bus (0..31).
gclkperiph	GCLK peripheral channel number m in PCHCTRLm (0..12).
inst	Instance number of the specified clock type.

Returns

Packed 32-bit clock subsystem identifier.

SUBSYS_TYPE_GCLKGEN

#define SUBSYS_TYPE_GCLKGEN   (4)

Subsystem type: Generic Clock Generator (GCLK GEN).

SUBSYS_TYPE_GCLKPERIPH

#define SUBSYS_TYPE_GCLKPERIPH   (5)

Subsystem type: Generic Clock Peripheral Channel (GCLK PERIPH).

SUBSYS_TYPE_MAX

#define SUBSYS_TYPE_MAX   (7)

Maximum valid subsystem type value.

This is the highest assigned subsystem type ID.

SUBSYS_TYPE_MCLKCPU

#define SUBSYS_TYPE_MCLKCPU   (6)

Subsystem type: Main Clock - CPU domain (MCLK CPU).

SUBSYS_TYPE_MCLKPERIPH

#define SUBSYS_TYPE_MCLKPERIPH   (7)

Subsystem type: Main Clock - peripheral domain (MCLK PERIPH).

SUBSYS_TYPE_OSC32K

#define SUBSYS_TYPE_OSC32K   (3)

Subsystem type: Internal 32 kHz oscillator (OSC32K).

SUBSYS_TYPE_OSCHF

#define SUBSYS_TYPE_OSCHF   (0)

Subsystem type: On-chip oscillator high frequency (OSCHF).

SUBSYS_TYPE_RTC

#define SUBSYS_TYPE_RTC   (1)

Subsystem type: Real-Time Counter (RTC).

SUBSYS_TYPE_XOSC32K

#define SUBSYS_TYPE_XOSC32K   (2)

Subsystem type: External 32 kHz crystal oscillator (XOSC32K).