memory-attr-arm64.h

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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_ARM64_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_ARM64_H_
 
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>


#define DT_MEM_ARM64_MASK               DT_MEM_ARCH_ATTR_MASK

#define DT_MEM_ARM64_GET(x)             ((x) & DT_MEM_ARM64_MASK)

#define DT_MEM_ARM64(x)         ((x) << DT_MEM_ARCH_ATTR_SHIFT)
 
/*
 * Architecture-specific sub-attribute bits (before shifting).
 *
 * These refine the generic DT_MEM_* attributes for ARM64.  They occupy
 * bits [31:20] of the zephyr,memory-attr value via DT_MEM_ARM64().
 */

#define ATTR_ARM64_CACHE_WB             BIT(1)
 
/*
 * Convenience macros: combinations of generic + arch-specific attributes.
 *
 * Following the subsystem's composable-bitmask design, each macro is
 * built from the generic DT_MEM_CACHEABLE flag and architecture-specific
 * sub-attributes rather than standalone one-hot enumerations.
 */

#define DT_MEM_ARM64_MMU_NORMAL_NC      (0)
#define DT_MEM_ARM64_MMU_NORMAL_WT      (DT_MEM_CACHEABLE)
#define DT_MEM_ARM64_MMU_NORMAL         (DT_MEM_CACHEABLE | \
                                         DT_MEM_ARM64(ATTR_ARM64_CACHE_WB))

#define DT_MEM_ARM64_MMU_UNKNOWN        DT_MEM_ARCH_ATTR_UNKNOWN

 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_ARM64_H_ */