mdio.h

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/*
 * Copyright 2023 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_NET_MDIO_H_
#define ZEPHYR_INCLUDE_NET_MDIO_H_

 
#ifdef __cplusplus
extern "C" {
#endif

enum mdio_opcode {
        MDIO_OP_C22_WRITE = 1,

        MDIO_OP_C22_READ = 2,

        MDIO_OP_C45_ADDRESS = 0,

        MDIO_OP_C45_WRITE = 1,

        MDIO_OP_C45_READ_INC = 2,

        MDIO_OP_C45_READ = 3
};
 
/* MDIO Manageable Device addresses */
#define MDIO_MMD_PMAPMD                 0x01U
#define MDIO_MMD_WIS                    0x02U
#define MDIO_MMD_PCS                    0x03U
#define MDIO_MMD_PHYXS                  0x04U
#define MDIO_MMD_DTEXS                  0x05U
#define MDIO_MMD_TC                     0x06U
#define MDIO_MMD_AN                     0x07U
#define MDIO_MMD_SEPARATED_PMA1         0x08U
#define MDIO_MMD_SEPARATED_PMA2         0x09U
#define MDIO_MMD_SEPARATED_PMA3         0x0AU
#define MDIO_MMD_SEPARATED_PMA4         0x0BU
#define MDIO_MMD_C22EXT                 0x1DU
#define MDIO_MMD_VENDOR_SPECIFIC1       0x1EU
#define MDIO_MMD_VENDOR_SPECIFIC2       0x1FU
 
/* MDIO generic registers */
#define MDIO_CTRL1                      0x0000U
#define MDIO_STAT1                      0x0001U
#define MDIO_DEVID1                     0x0002U
#define MDIO_DEVID2                     0x0003U
#define MDIO_SPEED                      0x0004U
#define MDIO_DEVS1                      0x0005U
#define MDIO_DEVS2                      0x0006U
#define MDIO_CTRL2                      0x0007U
#define MDIO_STAT2                      0x0008U
#define MDIO_PKGID1                     0x000EU
#define MDIO_PKGID2                     0x000FU
/* PCS Register: EEE capability Register */
#define MDIO_PCS_EEE_CAP                0x0014U
/* Auto-negotiation Register: EEE advertisement Register */
#define MDIO_AN_EEE_ADV                 0x003CU
 
 
/* BASE-T1 registers */
#define MDIO_AN_T1_CTRL                 0x0200U
#define MDIO_AN_T1_STAT                 0x0201U
#define MDIO_AN_T1_ADV_L                0x0202U
#define MDIO_AN_T1_ADV_M                0x0203U
#define MDIO_AN_T1_ADV_H                0x0204U
#define MDIO_AN_T1_LP_ADV_L             0x0205U
#define MDIO_AN_T1_LP_ADV_M             0x0206U
#define MDIO_AN_T1_LP_ADV_H             0x0207U

#define MDIO_PMA_PMD_BT1_CTRL           0x0834U
 
/* BASE-T1 Auto-negotiation Control register */
#define MDIO_AN_T1_CTRL_RESTART         BIT(9)
#define MDIO_AN_T1_CTRL_EN              BIT(12)
 
/* BASE-T1 Auto-negotiation Status register */
#define MDIO_AN_T1_STAT_LINK_STATUS     BIT(2)
#define MDIO_AN_T1_STAT_ABLE            BIT(3)
#define MDIO_AN_T1_STAT_REMOTE_FAULT    BIT(4)
#define MDIO_AN_T1_STAT_COMPLETE        BIT(5)
#define MDIO_AN_T1_STAT_PAGE_RX         BIT(6)
 
/* BASE-T1 Auto-negotiation Advertisement register [15:0] */
#define MDIO_AN_T1_ADV_L_PAUSE_CAP      BIT(10)
#define MDIO_AN_T1_ADV_L_PAUSE_ASYM     BIT(11)
#define MDIO_AN_T1_ADV_L_FORCE_MS       BIT(12)
#define MDIO_AN_T1_ADV_L_REMOTE_FAULT   BIT(13)
#define MDIO_AN_T1_ADV_L_ACK            BIT(14)
#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ  BIT(15)
 
/* BASE-T1 Auto-negotiation Advertisement register [31:16] */
#define MDIO_AN_T1_ADV_M_B10L           BIT(14)
#define MDIO_AN_T1_ADV_M_MST            BIT(4)
 
/* BASE-T1 Auto-negotiation Advertisement register [47:32] */
#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ  BIT(12)
#define MDIO_AN_T1_ADV_H_10L_TX_HI      BIT(13)
#define MDIO_AN_T1_ADV_H_10L_EEE        BIT(14)
 
/* BASE-T1 PMA/PMD control register */
#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST   BIT(14)
 
 
/* 10BASE-T1L registers */
#define MDIO_PMA_B10L_CTRL              0x08F6U
#define MDIO_PMA_B10L_STAT              0x08F7U
#define MDIO_PMA_B10L_TEST_CTRL         0x08F8U
#define MDIO_PMA_B10L_LINK_STAT         0x8302U
#define MDIO_PCS_B10L_CTRL              0x08E6U
#define MDIO_PCS_B10L_STAT              0x08E7U
 
/* 10BASE-T1L PMA control register */
#define MDIO_PMA_B10L_CTRL_TX_DIS_MODE_EN               BIT(14)
#define MDIO_PMA_B10L_CTRL_TX_LVL_HI                    BIT(12)
#define MDIO_PMA_B10L_CTRL_EEE                          BIT(10)
#define MDIO_PMA_B10L_CTRL_LB_PMA_LOC_EN                BIT(0)
 
/* 10BASE-T1L PMA status register */
#define MDIO_PMA_B10L_STAT_LINK                         BIT(0)
#define MDIO_PMA_B10L_STAT_FAULT                        BIT(1)
#define MDIO_PMA_B10L_STAT_POLARITY                     BIT(2)
#define MDIO_PMA_B10L_STAT_RECV_FAULT                   BIT(9)
#define MDIO_PMA_B10L_STAT_EEE                          BIT(10)
#define MDIO_PMA_B10L_STAT_LOW_POWER                    BIT(11)
#define MDIO_PMA_B10L_STAT_2V4_ABLE                     BIT(12)
#define MDIO_PMA_B10L_STAT_LB_ABLE                      BIT(13)
 
/* 10BASE-T1L test mode control register */
#define MDIO_PMA_B10L_TEST_CTRL_TEST_MODE_MASK          GENMASK(15, 13)
#define MDIO_PMA_B10L_TEST_CTRL_TEST_MODE_1             BIT(13)
#define MDIO_PMA_B10L_TEST_CTRL_TEST_MODE_2             BIT(14)
#define MDIO_PMA_B10L_TEST_CTRL_TEST_MODE_3             (BIT(13) | BIT(14))
 
/* 10BASE-T1L PMA link status*/
#define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK_LL     BIT(9)
#define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK        BIT(8)
#define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK_LL     BIT(7)
#define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK        BIT(6)
#define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK_LL         BIT(5)
#define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK            BIT(4)
#define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK_LL         BIT(1)
#define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK            BIT(0)
 
/* 10BASE-T1L PCS control */
#define MDIO_PCS_B10L_CTRL_LB_PCS_EN                    BIT(14)
 
/* 10BASE-T1L PCS status */
#define MDIO_PCS_B10L_STAT_DSCR_STAT_OK_LL              BIT(2)
 
/* Auto-negotiation Register: EEE advertisement Register */
#define MDIO_AN_EEE_ADV_1000T                           BIT(2)
#define MDIO_AN_EEE_ADV_100TX                           BIT(1)
 
#ifdef __cplusplus
}
#endif

 
#endif /* ZEPHYR_INCLUDE_NET_MDIO_H_ */