numaker_m48x_clock.h File Reference

Clock configuration macros for Nuvoton M48x series. More...

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Macros
HCLK clock source selection
#define	NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)
	Select HXT (external high-speed crystal) as HCLK clock source.
#define	NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)
	Select LXT (external low-speed crystal) as HCLK clock source.
#define	NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL   (0x2UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)
	Select PLL output as HCLK clock source.
#define	NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as HCLK clock source.
#define	NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as HCLK clock source.
SysTick clock source selection
#define	NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)
	Select HXT (external high-speed crystal) as SysTick clock source.
#define	NUMAKER_CLK_CLKSEL0_STCLKSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)
	Select LXT (external low-speed crystal) as SysTick clock source.
#define	NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT_DIV2   (0x2UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)
	Select HXT/2 as SysTick clock source.
#define	NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK_DIV2   (0x3UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)
	Select HCLK/2 as SysTick clock source.
#define	NUMAKER_CLK_CLKSEL0_STCLKSEL_HIRC_DIV2   (0x7UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)
	Select HIRC/2 as SysTick clock source.
#define	NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK   (0x01UL << SysTick_CTRL_CLKSOURCE_Pos)
	Select HCLK (system clock) as SysTick clock source.
camera capture interface clock source selection
#define	NUMAKER_CLK_CLKSEL0_CCAPSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)
	Select HXT (external high-speed crystal) as camera capture interface clock source.
#define	NUMAKER_CLK_CLKSEL0_CCAPSEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)
	Select PLL output as camera capture interface clock source.
#define	NUMAKER_CLK_CLKSEL0_CCAPSEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)
	Select HCLK (system clock) as camera capture interface clock source.
#define	NUMAKER_CLK_CLKSEL0_CCAPSEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as camera capture interface clock source.
SD host 0 clock source selection
#define	NUMAKER_CLK_CLKSEL0_SDH0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)
	Select HXT (external high-speed crystal) as SD host 0 clock source.
#define	NUMAKER_CLK_CLKSEL0_SDH0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)
	Select PLL output as SD host 0 clock source.
#define	NUMAKER_CLK_CLKSEL0_SDH0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as SD host 0 clock source.
#define	NUMAKER_CLK_CLKSEL0_SDH0SEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)
	Select HCLK (system clock) as SD host 0 clock source.
SD host 1 clock source selection
#define	NUMAKER_CLK_CLKSEL0_SDH1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)
	Select HXT (external high-speed crystal) as SD host 1 clock source.
#define	NUMAKER_CLK_CLKSEL0_SDH1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)
	Select PLL output as SD host 1 clock source.
#define	NUMAKER_CLK_CLKSEL0_SDH1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as SD host 1 clock source.
#define	NUMAKER_CLK_CLKSEL0_SDH1SEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)
	Select HCLK (system clock) as SD host 1 clock source.
USB clock source selection
#define	NUMAKER_CLK_CLKSEL0_USBSEL_RC48M   (0x0UL << NUMAKER_CLK_CLKSEL0_USBSEL_Pos)
	Select RC48M (48 MHz internal RC oscillator) as USB clock source.
#define	NUMAKER_CLK_CLKSEL0_USBSEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_USBSEL_Pos)
	Select PLL output as USB clock source.
watchdog timer clock source selection
#define	NUMAKER_CLK_CLKSEL1_WDTSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos)
	Select LXT (external low-speed crystal) as watchdog timer clock source.
#define	NUMAKER_CLK_CLKSEL1_WDTSEL_LIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as watchdog timer clock source.
#define	NUMAKER_CLK_CLKSEL1_WDTSEL_HCLK_DIV2048   (0x2UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos)
	Select HCLK/2048 as watchdog timer clock source.
Timer 0 clock source selection
#define	NUMAKER_CLK_CLKSEL1_TMR0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)
	Select HXT (external high-speed crystal) as Timer 0 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR0SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)
	Select LXT (external low-speed crystal) as Timer 0 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR0SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as Timer 0 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as Timer 0 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as Timer 0 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR0SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)
	Select external clock pin as Timer 0 clock source.
Timer 1 clock source selection
#define	NUMAKER_CLK_CLKSEL1_TMR1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)
	Select HXT (external high-speed crystal) as Timer 1 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR1SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)
	Select LXT (external low-speed crystal) as Timer 1 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR1SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as Timer 1 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR1SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as Timer 1 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR1SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as Timer 1 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR1SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)
	Select external clock pin as Timer 1 clock source.
Timer 2 clock source selection
#define	NUMAKER_CLK_CLKSEL1_TMR2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)
	Select HXT (external high-speed crystal) as Timer 2 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR2SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)
	Select LXT (external low-speed crystal) as Timer 2 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR2SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as Timer 2 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR2SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as Timer 2 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR2SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as Timer 2 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR2SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)
	Select external clock pin as Timer 2 clock source.
Timer 3 clock source selection
#define	NUMAKER_CLK_CLKSEL1_TMR3SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)
	Select HXT (external high-speed crystal) as Timer 3 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR3SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)
	Select LXT (external low-speed crystal) as Timer 3 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR3SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as Timer 3 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR3SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as Timer 3 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR3SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as Timer 3 clock source.
#define	NUMAKER_CLK_CLKSEL1_TMR3SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)
	Select external clock pin as Timer 3 clock source.
UART0 clock source selection
#define	NUMAKER_CLK_CLKSEL1_UART0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)
	Select HXT (external high-speed crystal) as UART0 clock source.
#define	NUMAKER_CLK_CLKSEL1_UART0SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)
	Select LXT (external low-speed crystal) as UART0 clock source.
#define	NUMAKER_CLK_CLKSEL1_UART0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)
	Select PLL output as UART0 clock source.
#define	NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART0 clock source.
UART1 clock source selection
#define	NUMAKER_CLK_CLKSEL1_UART1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)
	Select HXT (external high-speed crystal) as UART1 clock source.
#define	NUMAKER_CLK_CLKSEL1_UART1SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)
	Select LXT (external low-speed crystal) as UART1 clock source.
#define	NUMAKER_CLK_CLKSEL1_UART1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)
	Select PLL output as UART1 clock source.
#define	NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART1 clock source.
clock output clock source selection
#define	NUMAKER_CLK_CLKSEL1_CLKOSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)
	Select HXT (external high-speed crystal) as clock output clock source.
#define	NUMAKER_CLK_CLKSEL1_CLKOSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)
	Select LXT (external low-speed crystal) as clock output clock source.
#define	NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as clock output clock source.
#define	NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)
	Select HCLK (system clock) as clock output clock source.
window watchdog timer clock source selection
#define	NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_WWDTSEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as window watchdog timer clock source.
#define	NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048   (0x2UL << NUMAKER_CLK_CLKSEL1_WWDTSEL_Pos)
	Select HCLK/2048 as window watchdog timer clock source.
QSPI0 clock source selection
#define	NUMAKER_CLK_CLKSEL2_QSPI0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)
	Select HXT (external high-speed crystal) as QSPI0 clock source.
#define	NUMAKER_CLK_CLKSEL2_QSPI0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)
	Select PLL output as QSPI0 clock source.
#define	NUMAKER_CLK_CLKSEL2_QSPI0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as QSPI0 clock source.
#define	NUMAKER_CLK_CLKSEL2_QSPI0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as QSPI0 clock source.
SPI0 clock source selection
#define	NUMAKER_CLK_CLKSEL2_SPI0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)
	Select HXT (external high-speed crystal) as SPI0 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)
	Select PLL output as SPI0 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as SPI0 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI0SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as SPI0 clock source.
SPI1 clock source selection
#define	NUMAKER_CLK_CLKSEL2_SPI1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)
	Select HXT (external high-speed crystal) as SPI1 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)
	Select PLL output as SPI1 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as SPI1 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI1SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as SPI1 clock source.
EPWM0 clock source selection
#define	NUMAKER_CLK_CLKSEL2_EPWM0SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_EPWM0SEL_Pos)
	Select PLL output as EPWM0 clock source.
#define	NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0   (0x1UL << NUMAKER_CLK_CLKSEL2_EPWM0SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as EPWM0 clock source.
EPWM1 clock source selection
#define	NUMAKER_CLK_CLKSEL2_EPWM1SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_EPWM1SEL_Pos)
	Select PLL output as EPWM1 clock source.
#define	NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1   (0x1UL << NUMAKER_CLK_CLKSEL2_EPWM1SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as EPWM1 clock source.
BPWM0 clock source selection
#define	NUMAKER_CLK_CLKSEL2_BPWM0SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_BPWM0SEL_Pos)
	Select PLL output as BPWM0 clock source.
#define	NUMAKER_CLK_CLKSEL2_BPWM0SEL_PCLK0   (0x1UL << NUMAKER_CLK_CLKSEL2_BPWM0SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as BPWM0 clock source.
BPWM1 clock source selection
#define	NUMAKER_CLK_CLKSEL2_BPWM1SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_BPWM1SEL_Pos)
	Select PLL output as BPWM1 clock source.
#define	NUMAKER_CLK_CLKSEL2_BPWM1SEL_PCLK1   (0x1UL << NUMAKER_CLK_CLKSEL2_BPWM1SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as BPWM1 clock source.
SPI2 clock source selection
#define	NUMAKER_CLK_CLKSEL2_SPI2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)
	Select HXT (external high-speed crystal) as SPI2 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI2SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)
	Select PLL output as SPI2 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI2SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as SPI2 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI2SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as SPI2 clock source.
SPI3 clock source selection
#define	NUMAKER_CLK_CLKSEL2_SPI3SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)
	Select HXT (external high-speed crystal) as SPI3 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI3SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)
	Select PLL output as SPI3 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI3SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as SPI3 clock source.
#define	NUMAKER_CLK_CLKSEL2_SPI3SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as SPI3 clock source.
smart card 0 clock source selection
#define	NUMAKER_CLK_CLKSEL3_SC0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)
	Select HXT (external high-speed crystal) as smart card 0 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)
	Select PLL output as smart card 0 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as smart card 0 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as smart card 0 clock source.
smart card 1 clock source selection
#define	NUMAKER_CLK_CLKSEL3_SC1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)
	Select HXT (external high-speed crystal) as smart card 1 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)
	Select PLL output as smart card 1 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as smart card 1 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC1SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as smart card 1 clock source.
smart card 2 clock source selection
#define	NUMAKER_CLK_CLKSEL3_SC2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)
	Select HXT (external high-speed crystal) as smart card 2 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC2SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)
	Select PLL output as smart card 2 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC2SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as smart card 2 clock source.
#define	NUMAKER_CLK_CLKSEL3_SC2SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as smart card 2 clock source.
RTC clock source selection
#define	NUMAKER_CLK_CLKSEL3_RTCSEL_LXT   (0x0UL << NUMAKER_CLK_CLKSEL3_RTCSEL_Pos)
	Select LXT (external low-speed crystal) as RTC clock source.
#define	NUMAKER_CLK_CLKSEL3_RTCSEL_LIRC   (0x1UL << NUMAKER_CLK_CLKSEL3_RTCSEL_Pos)
	Select LIRC (internal low-speed RC oscillator) as RTC clock source.
QSPI1 clock source selection
#define	NUMAKER_CLK_CLKSEL3_QSPI1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)
	Select HXT (external high-speed crystal) as QSPI1 clock source.
#define	NUMAKER_CLK_CLKSEL3_QSPI1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)
	Select PLL output as QSPI1 clock source.
#define	NUMAKER_CLK_CLKSEL3_QSPI1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as QSPI1 clock source.
#define	NUMAKER_CLK_CLKSEL3_QSPI1SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)
	Select PCLK1 (APB1 peripheral clock) as QSPI1 clock source.
I2S0 clock source selection
#define	NUMAKER_CLK_CLKSEL3_I2S0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)
	Select HXT (external high-speed crystal) as I2S0 clock source.
#define	NUMAKER_CLK_CLKSEL3_I2S0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)
	Select PLL output as I2S0 clock source.
#define	NUMAKER_CLK_CLKSEL3_I2S0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as I2S0 clock source.
#define	NUMAKER_CLK_CLKSEL3_I2S0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)
	Select PCLK0 (APB0 peripheral clock) as I2S0 clock source.
UART2 clock source selection
#define	NUMAKER_CLK_CLKSEL3_UART2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)
	Select HXT (external high-speed crystal) as UART2 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART2SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)
	Select LXT (external low-speed crystal) as UART2 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART2SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)
	Select PLL output as UART2 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART2 clock source.
UART3 clock source selection
#define	NUMAKER_CLK_CLKSEL3_UART3SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)
	Select HXT (external high-speed crystal) as UART3 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART3SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)
	Select LXT (external low-speed crystal) as UART3 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART3SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)
	Select PLL output as UART3 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART3 clock source.
UART4 clock source selection
#define	NUMAKER_CLK_CLKSEL3_UART4SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)
	Select HXT (external high-speed crystal) as UART4 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART4SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)
	Select LXT (external low-speed crystal) as UART4 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART4SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)
	Select PLL output as UART4 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART4 clock source.
UART5 clock source selection
#define	NUMAKER_CLK_CLKSEL3_UART5SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)
	Select HXT (external high-speed crystal) as UART5 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART5SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)
	Select LXT (external low-speed crystal) as UART5 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART5SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)
	Select PLL output as UART5 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART5 clock source.
UART6 clock source selection
#define	NUMAKER_CLK_CLKSEL3_UART6SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)
	Select HXT (external high-speed crystal) as UART6 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART6SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)
	Select LXT (external low-speed crystal) as UART6 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART6SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)
	Select PLL output as UART6 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART6 clock source.
UART7 clock source selection
#define	NUMAKER_CLK_CLKSEL3_UART7SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)
	Select HXT (external high-speed crystal) as UART7 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART7SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)
	Select LXT (external low-speed crystal) as UART7 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART7SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)
	Select PLL output as UART7 clock source.
#define	NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)
	Select HIRC (internal high-speed RC oscillator) as UART7 clock source.
CLKDIV0 clock divider macros
#define	NUMAKER_CLK_CLKDIV0_HCLK(x)
	HCLK clock divider.
#define	NUMAKER_CLK_CLKDIV0_USB(x)
	USB clock divider.
#define	NUMAKER_CLK_CLKDIV0_SDH0(x)
	SD host 0 clock divider.
#define	NUMAKER_CLK_CLKDIV0_UART0(x)
	UART0 clock divider.
#define	NUMAKER_CLK_CLKDIV0_UART1(x)
	UART1 clock divider.
#define	NUMAKER_CLK_CLKDIV0_EADC(x)
	EADC clock divider.
CLKDIV1 clock divider macros
#define	NUMAKER_CLK_CLKDIV1_SC0(x)
	Smart card 0 clock divider.
#define	NUMAKER_CLK_CLKDIV1_SC1(x)
	Smart card 1 clock divider.
#define	NUMAKER_CLK_CLKDIV1_SC2(x)
	Smart card 2 clock divider.
CLKDIV2 clock divider macros
#define	NUMAKER_CLK_CLKDIV2_I2S0(x)
	I2S0 clock divider.
#define	NUMAKER_CLK_CLKDIV2_EADC1(x)
	EADC1 clock divider.
CLKDIV3 clock divider macros
#define	NUMAKER_CLK_CLKDIV3_CCAP(x)
	Camera capture clock divider.
#define	NUMAKER_CLK_CLKDIV3_VSENSE(x)
	Video sensor clock divider.
#define	NUMAKER_CLK_CLKDIV3_EMAC(x)
	Ethernet MAC clock divider.
#define	NUMAKER_CLK_CLKDIV3_SDH1(x)
	SD host 1 clock divider.
CLKDIV4 clock divider macros
#define	NUMAKER_CLK_CLKDIV4_UART2(x)
	UART2 clock divider.
#define	NUMAKER_CLK_CLKDIV4_UART3(x)
	UART3 clock divider.
#define	NUMAKER_CLK_CLKDIV4_UART4(x)
	UART4 clock divider.
#define	NUMAKER_CLK_CLKDIV4_UART5(x)
	UART5 clock divider.
#define	NUMAKER_CLK_CLKDIV4_UART6(x)
	UART6 clock divider.
#define	NUMAKER_CLK_CLKDIV4_UART7(x)
	UART7 clock divider.
PCLKDIV peripheral clock divider selection
#define	NUMAKER_CLK_PCLKDIV_PCLK0DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set PCLK0 to HCLK/1.
#define	NUMAKER_CLK_PCLKDIV_PCLK0DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set PCLK0 to HCLK/2.
#define	NUMAKER_CLK_PCLKDIV_PCLK0DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set PCLK0 to HCLK/4.
#define	NUMAKER_CLK_PCLKDIV_PCLK0DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set PCLK0 to HCLK/8.
#define	NUMAKER_CLK_PCLKDIV_PCLK0DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set PCLK0 to HCLK/16.
#define	NUMAKER_CLK_PCLKDIV_PCLK1DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set PCLK1 to HCLK/1.
#define	NUMAKER_CLK_PCLKDIV_PCLK1DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set PCLK1 to HCLK/2.
#define	NUMAKER_CLK_PCLKDIV_PCLK1DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set PCLK1 to HCLK/4.
#define	NUMAKER_CLK_PCLKDIV_PCLK1DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set PCLK1 to HCLK/8.
#define	NUMAKER_CLK_PCLKDIV_PCLK1DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set PCLK1 to HCLK/16.
#define	NUMAKER_CLK_PCLKDIV_APB0DIV_DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set APB0 clock to HCLK/1.
#define	NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set APB0 clock to HCLK/2.
#define	NUMAKER_CLK_PCLKDIV_APB0DIV_DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set APB0 clock to HCLK/4.
#define	NUMAKER_CLK_PCLKDIV_APB0DIV_DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set APB0 clock to HCLK/8.
#define	NUMAKER_CLK_PCLKDIV_APB0DIV_DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)
	Set APB0 clock to HCLK/16.
#define	NUMAKER_CLK_PCLKDIV_APB1DIV_DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set APB1 clock to HCLK/1.
#define	NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set APB1 clock to HCLK/2.
#define	NUMAKER_CLK_PCLKDIV_APB1DIV_DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set APB1 clock to HCLK/4.
#define	NUMAKER_CLK_PCLKDIV_APB1DIV_DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set APB1 clock to HCLK/8.
#define	NUMAKER_CLK_PCLKDIV_APB1DIV_DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)
	Set APB1 clock to HCLK/16.
Peripheral module clock configuration
#define	NUMAKER_PDMA_MODULE
	PDMA controller module clock configuration.
#define	NUMAKER_ISP_MODULE
	Flash ISP controller module clock configuration.
#define	NUMAKER_EBI_MODULE
	External bus interface module clock configuration.
#define	NUMAKER_USBH_MODULE
	USB host controller module clock configuration.
#define	NUMAKER_EMAC_MODULE
	Ethernet MAC controller module clock configuration.
#define	NUMAKER_SDH0_MODULE
	SD host 0 controller module clock configuration.
#define	NUMAKER_CRC_MODULE
	CRC generator module clock configuration.
#define	NUMAKER_CCAP_MODULE
	Camera capture interface module clock configuration.
#define	NUMAKER_SEN_MODULE
	Sensor interface module clock configuration.
#define	NUMAKER_HSUSBD_MODULE
	High-speed USB device controller module clock configuration.
#define	NUMAKER_CRPT_MODULE
	Cryptographic accelerator module clock configuration.
#define	NUMAKER_SPIM_MODULE
	SPI flash memory controller module clock configuration.
#define	NUMAKER_FMCIDLE_MODULE
	Flash memory controller idle module clock configuration.
#define	NUMAKER_SDH1_MODULE
	SD host 1 controller module clock configuration.
#define	NUMAKER_WDT_MODULE
	Watchdog timer module clock configuration.
#define	NUMAKER_RTC_MODULE
	Real-time clock module clock configuration.
#define	NUMAKER_TMR0_MODULE
	Timer 0 module clock configuration.
#define	NUMAKER_TMR1_MODULE
	Timer 1 module clock configuration.
#define	NUMAKER_TMR2_MODULE
	Timer 2 module clock configuration.
#define	NUMAKER_TMR3_MODULE
	Timer 3 module clock configuration.
#define	NUMAKER_CLKO_MODULE
	Clock frequency output module clock configuration.
#define	NUMAKER_WWDT_MODULE
	Window watchdog timer module clock configuration.
#define	NUMAKER_ACMP01_MODULE
	Analog comparator 0/1 module clock configuration.
#define	NUMAKER_I2C0_MODULE
	I2C0 module clock configuration.
#define	NUMAKER_I2C1_MODULE
	I2C1 module clock configuration.
#define	NUMAKER_I2C2_MODULE
	I2C2 module clock configuration.
#define	NUMAKER_QSPI0_MODULE
	QSPI0 module clock configuration.
#define	NUMAKER_SPI0_MODULE
	SPI0 module clock configuration.
#define	NUMAKER_SPI1_MODULE
	SPI1 module clock configuration.
#define	NUMAKER_SPI2_MODULE
	SPI2 module clock configuration.
#define	NUMAKER_UART0_MODULE
	UART0 module clock configuration.
#define	NUMAKER_UART1_MODULE
	UART1 module clock configuration.
#define	NUMAKER_UART2_MODULE
	UART2 module clock configuration.
#define	NUMAKER_UART3_MODULE
	UART3 module clock configuration.
#define	NUMAKER_UART4_MODULE
	UART4 module clock configuration.
#define	NUMAKER_UART5_MODULE
	UART5 module clock configuration.
#define	NUMAKER_UART6_MODULE
	UART6 module clock configuration.
#define	NUMAKER_UART7_MODULE
	UART7 module clock configuration.
#define	NUMAKER_CAN0_MODULE
	CAN0 module clock configuration.
#define	NUMAKER_CAN1_MODULE
	CAN1 module clock configuration.
#define	NUMAKER_OTG_MODULE
	USB OTG module clock configuration.
#define	NUMAKER_USBD_MODULE
	USB device controller module clock configuration.
#define	NUMAKER_EADC_MODULE
	Enhanced ADC 0 module clock configuration.
#define	NUMAKER_I2S0_MODULE
	I2S0 audio interface module clock configuration.
#define	NUMAKER_HSOTG_MODULE
	High-speed USB OTG module clock configuration.
#define	NUMAKER_SC0_MODULE
	Smart card 0 interface module clock configuration.
#define	NUMAKER_SC1_MODULE
	Smart card 1 interface module clock configuration.
#define	NUMAKER_SC2_MODULE
	Smart card 2 interface module clock configuration.
#define	NUMAKER_QSPI1_MODULE
	QSPI1 module clock configuration.
#define	NUMAKER_SPI3_MODULE
	SPI3 module clock configuration.
#define	NUMAKER_USCI0_MODULE
	USCI0 module clock configuration.
#define	NUMAKER_USCI1_MODULE
	USCI1 module clock configuration.
#define	NUMAKER_DAC_MODULE
	DAC module clock configuration.
#define	NUMAKER_CAN2_MODULE
	CAN2 module clock configuration.
#define	NUMAKER_EPWM0_MODULE
	EPWM0 module clock configuration.
#define	NUMAKER_EPWM1_MODULE
	EPWM1 module clock configuration.
#define	NUMAKER_BPWM0_MODULE
	Basic PWM 0 module clock configuration.
#define	NUMAKER_BPWM1_MODULE
	Basic PWM 1 module clock configuration.
#define	NUMAKER_QEI0_MODULE
	Quadrature encoder 0 module clock configuration.
#define	NUMAKER_QEI1_MODULE
	Quadrature encoder 1 module clock configuration.
#define	NUMAKER_TRNG_MODULE
	True random number generator module clock configuration.
#define	NUMAKER_ECAP0_MODULE
	Enhanced input capture 0 module clock configuration.
#define	NUMAKER_ECAP1_MODULE
	Enhanced input capture 1 module clock configuration.
#define	NUMAKER_OPA_MODULE
	Operational amplifier module clock configuration.
#define	NUMAKER_EADC1_MODULE
	Enhanced ADC 1 module clock configuration.
PMU power-down mode selection
#define	NUMAKER_CLK_PMUCTL_PDMSEL_PD   0x00000000
	Normal power-down mode.
#define	NUMAKER_CLK_PMUCTL_PDMSEL_LLPD   0x00000001
	Low leakage power-down mode.
#define	NUMAKER_CLK_PMUCTL_PDMSEL_FWPD   0x00000002
	Fast wake-up power-down mode.
#define	NUMAKER_CLK_PMUCTL_PDMSEL_SPD   0x00000004
	Standby power-down mode.
#define	NUMAKER_CLK_PMUCTL_PDMSEL_DPD   0x00000006
	Deep power-down mode.

Detailed Description

Clock configuration macros for Nuvoton M48x series.

Provides clock source selection, clock divider, peripheral module clock enable, and power management macros for the Nuvoton M480 series SoC family. These macros encode CLK controller register fields for use in devicetree clock property assignments.

Macro Definition Documentation

NUMAKER_ACMP01_MODULE

#define NUMAKER_ACMP01_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (7UL << 0))

Analog comparator 0/1 module clock configuration.

NUMAKER_BPWM0_MODULE

#define NUMAKER_BPWM0_MODULE

Value:

((2UL << 30) | (2UL << 28) | (0x1UL << 25) | (8UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (18UL << 0))

Basic PWM 0 module clock configuration.

NUMAKER_BPWM1_MODULE

#define NUMAKER_BPWM1_MODULE

Value:

((2UL << 30) | (2UL << 28) | (0x1UL << 25) | (9UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (19UL << 0))

Basic PWM 1 module clock configuration.

NUMAKER_CAN0_MODULE

#define NUMAKER_CAN0_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (24UL << 0))

CAN0 module clock configuration.

NUMAKER_CAN1_MODULE

#define NUMAKER_CAN1_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (25UL << 0))

CAN1 module clock configuration.

NUMAKER_CAN2_MODULE

#define NUMAKER_CAN2_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (28UL << 0))

CAN2 module clock configuration.

NUMAKER_CCAP_MODULE

#define NUMAKER_CCAP_MODULE

Value:

((0UL << 30) | (0UL << 28) | (0x3UL << 25) | (16UL << 20) | (2UL << 18) | (0xFFUL << 10) | \
 (0UL << 5) | (8UL << 0))

Camera capture interface module clock configuration.

NUMAKER_CLK_CLKDIV0_EADC

#define NUMAKER_CLK_CLKDIV0_EADC

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV0_EADCDIV_Pos)

EADC clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV0_HCLK

#define NUMAKER_CLK_CLKDIV0_HCLK

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV0_HCLKDIV_Pos)

HCLK clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV0_SDH0

#define NUMAKER_CLK_CLKDIV0_SDH0

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV0_SDH0DIV_Pos)

SD host 0 clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV0_UART0

#define NUMAKER_CLK_CLKDIV0_UART0

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV0_UART0DIV_Pos)

UART0 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV0_UART1

#define NUMAKER_CLK_CLKDIV0_UART1

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV0_UART1DIV_Pos)

UART1 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV0_USB

#define NUMAKER_CLK_CLKDIV0_USB

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV0_USBDIV_Pos)

USB clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV1_SC0

#define NUMAKER_CLK_CLKDIV1_SC0

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV1_SC0DIV_Pos)

Smart card 0 clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV1_SC1

#define NUMAKER_CLK_CLKDIV1_SC1

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV1_SC1DIV_Pos)

Smart card 1 clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV1_SC2

#define NUMAKER_CLK_CLKDIV1_SC2

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV1_SC2DIV_Pos)

Smart card 2 clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV2_EADC1

#define NUMAKER_CLK_CLKDIV2_EADC1

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV2_EADC1DIV_Pos)

EADC1 clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV2_I2S0

#define NUMAKER_CLK_CLKDIV2_I2S0

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV2_I2S0DIV_Pos)

I2S0 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV3_CCAP

#define NUMAKER_CLK_CLKDIV3_CCAP

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV3_CCAPDIV_Pos)

Camera capture clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV3_EMAC

#define NUMAKER_CLK_CLKDIV3_EMAC

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV3_EMACDIV_Pos)

Ethernet MAC clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV3_SDH1

#define NUMAKER_CLK_CLKDIV3_SDH1

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV3_SDH1DIV_Pos)

SD host 1 clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV3_VSENSE

#define NUMAKER_CLK_CLKDIV3_VSENSE

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV3_VSENSEDIV_Pos)

Video sensor clock divider.

x is the divider value (1..256)

NUMAKER_CLK_CLKDIV4_UART2

#define NUMAKER_CLK_CLKDIV4_UART2

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV4_UART2DIV_Pos)

UART2 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV4_UART3

#define NUMAKER_CLK_CLKDIV4_UART3

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV4_UART3DIV_Pos)

UART3 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV4_UART4

#define NUMAKER_CLK_CLKDIV4_UART4

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV4_UART4DIV_Pos)

UART4 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV4_UART5

#define NUMAKER_CLK_CLKDIV4_UART5

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV4_UART5DIV_Pos)

UART5 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV4_UART6

#define NUMAKER_CLK_CLKDIV4_UART6

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV4_UART6DIV_Pos)

UART6 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKDIV4_UART7

#define NUMAKER_CLK_CLKDIV4_UART7

(

x

)

Value:

(((x) - 1UL) << NUMAKER_CLK_CLKDIV4_UART7DIV_Pos)

UART7 clock divider.

x is the divider value (1..16)

NUMAKER_CLK_CLKSEL0_CCAPSEL_HCLK

#define NUMAKER_CLK_CLKSEL0_CCAPSEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)

Select HCLK (system clock) as camera capture interface clock source.

NUMAKER_CLK_CLKSEL0_CCAPSEL_HIRC

#define NUMAKER_CLK_CLKSEL0_CCAPSEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)

Select HIRC (internal high-speed RC oscillator) as camera capture interface clock source.

NUMAKER_CLK_CLKSEL0_CCAPSEL_HXT

#define NUMAKER_CLK_CLKSEL0_CCAPSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)

Select HXT (external high-speed crystal) as camera capture interface clock source.

NUMAKER_CLK_CLKSEL0_CCAPSEL_PLL

#define NUMAKER_CLK_CLKSEL0_CCAPSEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_CCAPSEL_Pos)

Select PLL output as camera capture interface clock source.

NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC

#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)

Select HIRC (internal high-speed RC oscillator) as HCLK clock source.

NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT

#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)

Select HXT (external high-speed crystal) as HCLK clock source.

NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC

#define NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)

Select LIRC (internal low-speed RC oscillator) as HCLK clock source.

NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT

#define NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)

Select LXT (external low-speed crystal) as HCLK clock source.

NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL

#define NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL   (0x2UL << NUMAKER_CLK_CLKSEL0_HCLKSEL_Pos)

Select PLL output as HCLK clock source.

NUMAKER_CLK_CLKSEL0_SDH0SEL_HCLK

#define NUMAKER_CLK_CLKSEL0_SDH0SEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)

Select HCLK (system clock) as SD host 0 clock source.

NUMAKER_CLK_CLKSEL0_SDH0SEL_HIRC

#define NUMAKER_CLK_CLKSEL0_SDH0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as SD host 0 clock source.

NUMAKER_CLK_CLKSEL0_SDH0SEL_HXT

#define NUMAKER_CLK_CLKSEL0_SDH0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)

Select HXT (external high-speed crystal) as SD host 0 clock source.

NUMAKER_CLK_CLKSEL0_SDH0SEL_PLL

#define NUMAKER_CLK_CLKSEL0_SDH0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_SDH0SEL_Pos)

Select PLL output as SD host 0 clock source.

NUMAKER_CLK_CLKSEL0_SDH1SEL_HCLK

#define NUMAKER_CLK_CLKSEL0_SDH1SEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)

Select HCLK (system clock) as SD host 1 clock source.

NUMAKER_CLK_CLKSEL0_SDH1SEL_HIRC

#define NUMAKER_CLK_CLKSEL0_SDH1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as SD host 1 clock source.

NUMAKER_CLK_CLKSEL0_SDH1SEL_HXT

#define NUMAKER_CLK_CLKSEL0_SDH1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)

Select HXT (external high-speed crystal) as SD host 1 clock source.

NUMAKER_CLK_CLKSEL0_SDH1SEL_PLL

#define NUMAKER_CLK_CLKSEL0_SDH1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_SDH1SEL_Pos)

Select PLL output as SD host 1 clock source.

NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK

#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK   (0x01UL << SysTick_CTRL_CLKSOURCE_Pos)

Select HCLK (system clock) as SysTick clock source.

NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK_DIV2

#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK_DIV2   (0x3UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)

Select HCLK/2 as SysTick clock source.

NUMAKER_CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HIRC_DIV2   (0x7UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)

Select HIRC/2 as SysTick clock source.

NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT

#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)

Select HXT (external high-speed crystal) as SysTick clock source.

NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT_DIV2

#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT_DIV2   (0x2UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)

Select HXT/2 as SysTick clock source.

NUMAKER_CLK_CLKSEL0_STCLKSEL_LXT

#define NUMAKER_CLK_CLKSEL0_STCLKSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL0_STCLKSEL_Pos)

Select LXT (external low-speed crystal) as SysTick clock source.

NUMAKER_CLK_CLKSEL0_USBSEL_PLL

#define NUMAKER_CLK_CLKSEL0_USBSEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL0_USBSEL_Pos)

Select PLL output as USB clock source.

NUMAKER_CLK_CLKSEL0_USBSEL_RC48M

#define NUMAKER_CLK_CLKSEL0_USBSEL_RC48M   (0x0UL << NUMAKER_CLK_CLKSEL0_USBSEL_Pos)

Select RC48M (48 MHz internal RC oscillator) as USB clock source.

NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK

#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK   (0x2UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)

Select HCLK (system clock) as clock output clock source.

NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC

#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)

Select HIRC (internal high-speed RC oscillator) as clock output clock source.

NUMAKER_CLK_CLKSEL1_CLKOSEL_HXT

#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)

Select HXT (external high-speed crystal) as clock output clock source.

NUMAKER_CLK_CLKSEL1_CLKOSEL_LXT

#define NUMAKER_CLK_CLKSEL1_CLKOSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_CLKOSEL_Pos)

Select LXT (external low-speed crystal) as clock output clock source.

NUMAKER_CLK_CLKSEL1_TMR0SEL_EXT

#define NUMAKER_CLK_CLKSEL1_TMR0SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)

Select external clock pin as Timer 0 clock source.

NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC

#define NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as Timer 0 clock source.

NUMAKER_CLK_CLKSEL1_TMR0SEL_HXT

#define NUMAKER_CLK_CLKSEL1_TMR0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)

Select HXT (external high-speed crystal) as Timer 0 clock source.

NUMAKER_CLK_CLKSEL1_TMR0SEL_LIRC

#define NUMAKER_CLK_CLKSEL1_TMR0SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)

Select LIRC (internal low-speed RC oscillator) as Timer 0 clock source.

NUMAKER_CLK_CLKSEL1_TMR0SEL_LXT

#define NUMAKER_CLK_CLKSEL1_TMR0SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)

Select LXT (external low-speed crystal) as Timer 0 clock source.

NUMAKER_CLK_CLKSEL1_TMR0SEL_PCLK0

#define NUMAKER_CLK_CLKSEL1_TMR0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR0SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as Timer 0 clock source.

NUMAKER_CLK_CLKSEL1_TMR1SEL_EXT

#define NUMAKER_CLK_CLKSEL1_TMR1SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)

Select external clock pin as Timer 1 clock source.

NUMAKER_CLK_CLKSEL1_TMR1SEL_HIRC

#define NUMAKER_CLK_CLKSEL1_TMR1SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as Timer 1 clock source.

NUMAKER_CLK_CLKSEL1_TMR1SEL_HXT

#define NUMAKER_CLK_CLKSEL1_TMR1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)

Select HXT (external high-speed crystal) as Timer 1 clock source.

NUMAKER_CLK_CLKSEL1_TMR1SEL_LIRC

#define NUMAKER_CLK_CLKSEL1_TMR1SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)

Select LIRC (internal low-speed RC oscillator) as Timer 1 clock source.

NUMAKER_CLK_CLKSEL1_TMR1SEL_LXT

#define NUMAKER_CLK_CLKSEL1_TMR1SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)

Select LXT (external low-speed crystal) as Timer 1 clock source.

NUMAKER_CLK_CLKSEL1_TMR1SEL_PCLK0

#define NUMAKER_CLK_CLKSEL1_TMR1SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR1SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as Timer 1 clock source.

NUMAKER_CLK_CLKSEL1_TMR2SEL_EXT

#define NUMAKER_CLK_CLKSEL1_TMR2SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)

Select external clock pin as Timer 2 clock source.

NUMAKER_CLK_CLKSEL1_TMR2SEL_HIRC

#define NUMAKER_CLK_CLKSEL1_TMR2SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as Timer 2 clock source.

NUMAKER_CLK_CLKSEL1_TMR2SEL_HXT

#define NUMAKER_CLK_CLKSEL1_TMR2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)

Select HXT (external high-speed crystal) as Timer 2 clock source.

NUMAKER_CLK_CLKSEL1_TMR2SEL_LIRC

#define NUMAKER_CLK_CLKSEL1_TMR2SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)

Select LIRC (internal low-speed RC oscillator) as Timer 2 clock source.

NUMAKER_CLK_CLKSEL1_TMR2SEL_LXT

#define NUMAKER_CLK_CLKSEL1_TMR2SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)

Select LXT (external low-speed crystal) as Timer 2 clock source.

NUMAKER_CLK_CLKSEL1_TMR2SEL_PCLK1

#define NUMAKER_CLK_CLKSEL1_TMR2SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR2SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as Timer 2 clock source.

NUMAKER_CLK_CLKSEL1_TMR3SEL_EXT

#define NUMAKER_CLK_CLKSEL1_TMR3SEL_EXT   (0x3UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)

Select external clock pin as Timer 3 clock source.

NUMAKER_CLK_CLKSEL1_TMR3SEL_HIRC

#define NUMAKER_CLK_CLKSEL1_TMR3SEL_HIRC   (0x7UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as Timer 3 clock source.

NUMAKER_CLK_CLKSEL1_TMR3SEL_HXT

#define NUMAKER_CLK_CLKSEL1_TMR3SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)

Select HXT (external high-speed crystal) as Timer 3 clock source.

NUMAKER_CLK_CLKSEL1_TMR3SEL_LIRC

#define NUMAKER_CLK_CLKSEL1_TMR3SEL_LIRC   (0x5UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)

Select LIRC (internal low-speed RC oscillator) as Timer 3 clock source.

NUMAKER_CLK_CLKSEL1_TMR3SEL_LXT

#define NUMAKER_CLK_CLKSEL1_TMR3SEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)

Select LXT (external low-speed crystal) as Timer 3 clock source.

NUMAKER_CLK_CLKSEL1_TMR3SEL_PCLK1

#define NUMAKER_CLK_CLKSEL1_TMR3SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL1_TMR3SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as Timer 3 clock source.

NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC

#define NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART0 clock source.

NUMAKER_CLK_CLKSEL1_UART0SEL_HXT

#define NUMAKER_CLK_CLKSEL1_UART0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)

Select HXT (external high-speed crystal) as UART0 clock source.

NUMAKER_CLK_CLKSEL1_UART0SEL_LXT

#define NUMAKER_CLK_CLKSEL1_UART0SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)

Select LXT (external low-speed crystal) as UART0 clock source.

NUMAKER_CLK_CLKSEL1_UART0SEL_PLL

#define NUMAKER_CLK_CLKSEL1_UART0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL1_UART0SEL_Pos)

Select PLL output as UART0 clock source.

NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC

#define NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART1 clock source.

NUMAKER_CLK_CLKSEL1_UART1SEL_HXT

#define NUMAKER_CLK_CLKSEL1_UART1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)

Select HXT (external high-speed crystal) as UART1 clock source.

NUMAKER_CLK_CLKSEL1_UART1SEL_LXT

#define NUMAKER_CLK_CLKSEL1_UART1SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)

Select LXT (external low-speed crystal) as UART1 clock source.

NUMAKER_CLK_CLKSEL1_UART1SEL_PLL

#define NUMAKER_CLK_CLKSEL1_UART1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL1_UART1SEL_Pos)

Select PLL output as UART1 clock source.

NUMAKER_CLK_CLKSEL1_WDTSEL_HCLK_DIV2048

#define NUMAKER_CLK_CLKSEL1_WDTSEL_HCLK_DIV2048   (0x2UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos)

Select HCLK/2048 as watchdog timer clock source.

NUMAKER_CLK_CLKSEL1_WDTSEL_LIRC

#define NUMAKER_CLK_CLKSEL1_WDTSEL_LIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos)

Select LIRC (internal low-speed RC oscillator) as watchdog timer clock source.

NUMAKER_CLK_CLKSEL1_WDTSEL_LXT

#define NUMAKER_CLK_CLKSEL1_WDTSEL_LXT   (0x1UL << NUMAKER_CLK_CLKSEL1_WDTSEL_Pos)

Select LXT (external low-speed crystal) as watchdog timer clock source.

NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048

#define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048   (0x2UL << NUMAKER_CLK_CLKSEL1_WWDTSEL_Pos)

Select HCLK/2048 as window watchdog timer clock source.

NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC

#define NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC   (0x3UL << NUMAKER_CLK_CLKSEL1_WWDTSEL_Pos)

Select LIRC (internal low-speed RC oscillator) as window watchdog timer clock source.

NUMAKER_CLK_CLKSEL2_BPWM0SEL_PCLK0

#define NUMAKER_CLK_CLKSEL2_BPWM0SEL_PCLK0   (0x1UL << NUMAKER_CLK_CLKSEL2_BPWM0SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as BPWM0 clock source.

NUMAKER_CLK_CLKSEL2_BPWM0SEL_PLL

#define NUMAKER_CLK_CLKSEL2_BPWM0SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_BPWM0SEL_Pos)

Select PLL output as BPWM0 clock source.

NUMAKER_CLK_CLKSEL2_BPWM1SEL_PCLK1

#define NUMAKER_CLK_CLKSEL2_BPWM1SEL_PCLK1   (0x1UL << NUMAKER_CLK_CLKSEL2_BPWM1SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as BPWM1 clock source.

NUMAKER_CLK_CLKSEL2_BPWM1SEL_PLL

#define NUMAKER_CLK_CLKSEL2_BPWM1SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_BPWM1SEL_Pos)

Select PLL output as BPWM1 clock source.

NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0

#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0   (0x1UL << NUMAKER_CLK_CLKSEL2_EPWM0SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as EPWM0 clock source.

NUMAKER_CLK_CLKSEL2_EPWM0SEL_PLL

#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_EPWM0SEL_Pos)

Select PLL output as EPWM0 clock source.

NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1

#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1   (0x1UL << NUMAKER_CLK_CLKSEL2_EPWM1SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as EPWM1 clock source.

NUMAKER_CLK_CLKSEL2_EPWM1SEL_PLL

#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_PLL   (0x0UL << NUMAKER_CLK_CLKSEL2_EPWM1SEL_Pos)

Select PLL output as EPWM1 clock source.

NUMAKER_CLK_CLKSEL2_QSPI0SEL_HIRC

#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as QSPI0 clock source.

NUMAKER_CLK_CLKSEL2_QSPI0SEL_HXT

#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)

Select HXT (external high-speed crystal) as QSPI0 clock source.

NUMAKER_CLK_CLKSEL2_QSPI0SEL_PCLK0

#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as QSPI0 clock source.

NUMAKER_CLK_CLKSEL2_QSPI0SEL_PLL

#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_QSPI0SEL_Pos)

Select PLL output as QSPI0 clock source.

NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC

#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as SPI0 clock source.

NUMAKER_CLK_CLKSEL2_SPI0SEL_HXT

#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)

Select HXT (external high-speed crystal) as SPI0 clock source.

NUMAKER_CLK_CLKSEL2_SPI0SEL_PCLK1

#define NUMAKER_CLK_CLKSEL2_SPI0SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as SPI0 clock source.

NUMAKER_CLK_CLKSEL2_SPI0SEL_PLL

#define NUMAKER_CLK_CLKSEL2_SPI0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI0SEL_Pos)

Select PLL output as SPI0 clock source.

NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC

#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as SPI1 clock source.

NUMAKER_CLK_CLKSEL2_SPI1SEL_HXT

#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)

Select HXT (external high-speed crystal) as SPI1 clock source.

NUMAKER_CLK_CLKSEL2_SPI1SEL_PCLK0

#define NUMAKER_CLK_CLKSEL2_SPI1SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as SPI1 clock source.

NUMAKER_CLK_CLKSEL2_SPI1SEL_PLL

#define NUMAKER_CLK_CLKSEL2_SPI1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI1SEL_Pos)

Select PLL output as SPI1 clock source.

NUMAKER_CLK_CLKSEL2_SPI2SEL_HIRC

#define NUMAKER_CLK_CLKSEL2_SPI2SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as SPI2 clock source.

NUMAKER_CLK_CLKSEL2_SPI2SEL_HXT

#define NUMAKER_CLK_CLKSEL2_SPI2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)

Select HXT (external high-speed crystal) as SPI2 clock source.

NUMAKER_CLK_CLKSEL2_SPI2SEL_PCLK1

#define NUMAKER_CLK_CLKSEL2_SPI2SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as SPI2 clock source.

NUMAKER_CLK_CLKSEL2_SPI2SEL_PLL

#define NUMAKER_CLK_CLKSEL2_SPI2SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI2SEL_Pos)

Select PLL output as SPI2 clock source.

NUMAKER_CLK_CLKSEL2_SPI3SEL_HIRC

#define NUMAKER_CLK_CLKSEL2_SPI3SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as SPI3 clock source.

NUMAKER_CLK_CLKSEL2_SPI3SEL_HXT

#define NUMAKER_CLK_CLKSEL2_SPI3SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)

Select HXT (external high-speed crystal) as SPI3 clock source.

NUMAKER_CLK_CLKSEL2_SPI3SEL_PCLK0

#define NUMAKER_CLK_CLKSEL2_SPI3SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as SPI3 clock source.

NUMAKER_CLK_CLKSEL2_SPI3SEL_PLL

#define NUMAKER_CLK_CLKSEL2_SPI3SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL2_SPI3SEL_Pos)

Select PLL output as SPI3 clock source.

NUMAKER_CLK_CLKSEL3_I2S0SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_I2S0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as I2S0 clock source.

NUMAKER_CLK_CLKSEL3_I2S0SEL_HXT

#define NUMAKER_CLK_CLKSEL3_I2S0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)

Select HXT (external high-speed crystal) as I2S0 clock source.

NUMAKER_CLK_CLKSEL3_I2S0SEL_PCLK0

#define NUMAKER_CLK_CLKSEL3_I2S0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as I2S0 clock source.

NUMAKER_CLK_CLKSEL3_I2S0SEL_PLL

#define NUMAKER_CLK_CLKSEL3_I2S0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_I2S0SEL_Pos)

Select PLL output as I2S0 clock source.

NUMAKER_CLK_CLKSEL3_QSPI1SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_QSPI1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as QSPI1 clock source.

NUMAKER_CLK_CLKSEL3_QSPI1SEL_HXT

#define NUMAKER_CLK_CLKSEL3_QSPI1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)

Select HXT (external high-speed crystal) as QSPI1 clock source.

NUMAKER_CLK_CLKSEL3_QSPI1SEL_PCLK1

#define NUMAKER_CLK_CLKSEL3_QSPI1SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as QSPI1 clock source.

NUMAKER_CLK_CLKSEL3_QSPI1SEL_PLL

#define NUMAKER_CLK_CLKSEL3_QSPI1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_QSPI1SEL_Pos)

Select PLL output as QSPI1 clock source.

NUMAKER_CLK_CLKSEL3_RTCSEL_LIRC

#define NUMAKER_CLK_CLKSEL3_RTCSEL_LIRC   (0x1UL << NUMAKER_CLK_CLKSEL3_RTCSEL_Pos)

Select LIRC (internal low-speed RC oscillator) as RTC clock source.

NUMAKER_CLK_CLKSEL3_RTCSEL_LXT

#define NUMAKER_CLK_CLKSEL3_RTCSEL_LXT   (0x0UL << NUMAKER_CLK_CLKSEL3_RTCSEL_Pos)

Select LXT (external low-speed crystal) as RTC clock source.

NUMAKER_CLK_CLKSEL3_SC0SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_SC0SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as smart card 0 clock source.

NUMAKER_CLK_CLKSEL3_SC0SEL_HXT

#define NUMAKER_CLK_CLKSEL3_SC0SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)

Select HXT (external high-speed crystal) as smart card 0 clock source.

NUMAKER_CLK_CLKSEL3_SC0SEL_PCLK0

#define NUMAKER_CLK_CLKSEL3_SC0SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as smart card 0 clock source.

NUMAKER_CLK_CLKSEL3_SC0SEL_PLL

#define NUMAKER_CLK_CLKSEL3_SC0SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_SC0SEL_Pos)

Select PLL output as smart card 0 clock source.

NUMAKER_CLK_CLKSEL3_SC1SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_SC1SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as smart card 1 clock source.

NUMAKER_CLK_CLKSEL3_SC1SEL_HXT

#define NUMAKER_CLK_CLKSEL3_SC1SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)

Select HXT (external high-speed crystal) as smart card 1 clock source.

NUMAKER_CLK_CLKSEL3_SC1SEL_PCLK1

#define NUMAKER_CLK_CLKSEL3_SC1SEL_PCLK1   (0x2UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)

Select PCLK1 (APB1 peripheral clock) as smart card 1 clock source.

NUMAKER_CLK_CLKSEL3_SC1SEL_PLL

#define NUMAKER_CLK_CLKSEL3_SC1SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_SC1SEL_Pos)

Select PLL output as smart card 1 clock source.

NUMAKER_CLK_CLKSEL3_SC2SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_SC2SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as smart card 2 clock source.

NUMAKER_CLK_CLKSEL3_SC2SEL_HXT

#define NUMAKER_CLK_CLKSEL3_SC2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)

Select HXT (external high-speed crystal) as smart card 2 clock source.

NUMAKER_CLK_CLKSEL3_SC2SEL_PCLK0

#define NUMAKER_CLK_CLKSEL3_SC2SEL_PCLK0   (0x2UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)

Select PCLK0 (APB0 peripheral clock) as smart card 2 clock source.

NUMAKER_CLK_CLKSEL3_SC2SEL_PLL

#define NUMAKER_CLK_CLKSEL3_SC2SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_SC2SEL_Pos)

Select PLL output as smart card 2 clock source.

NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART2 clock source.

NUMAKER_CLK_CLKSEL3_UART2SEL_HXT

#define NUMAKER_CLK_CLKSEL3_UART2SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)

Select HXT (external high-speed crystal) as UART2 clock source.

NUMAKER_CLK_CLKSEL3_UART2SEL_LXT

#define NUMAKER_CLK_CLKSEL3_UART2SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)

Select LXT (external low-speed crystal) as UART2 clock source.

NUMAKER_CLK_CLKSEL3_UART2SEL_PLL

#define NUMAKER_CLK_CLKSEL3_UART2SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART2SEL_Pos)

Select PLL output as UART2 clock source.

NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART3 clock source.

NUMAKER_CLK_CLKSEL3_UART3SEL_HXT

#define NUMAKER_CLK_CLKSEL3_UART3SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)

Select HXT (external high-speed crystal) as UART3 clock source.

NUMAKER_CLK_CLKSEL3_UART3SEL_LXT

#define NUMAKER_CLK_CLKSEL3_UART3SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)

Select LXT (external low-speed crystal) as UART3 clock source.

NUMAKER_CLK_CLKSEL3_UART3SEL_PLL

#define NUMAKER_CLK_CLKSEL3_UART3SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART3SEL_Pos)

Select PLL output as UART3 clock source.

NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART4 clock source.

NUMAKER_CLK_CLKSEL3_UART4SEL_HXT

#define NUMAKER_CLK_CLKSEL3_UART4SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)

Select HXT (external high-speed crystal) as UART4 clock source.

NUMAKER_CLK_CLKSEL3_UART4SEL_LXT

#define NUMAKER_CLK_CLKSEL3_UART4SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)

Select LXT (external low-speed crystal) as UART4 clock source.

NUMAKER_CLK_CLKSEL3_UART4SEL_PLL

#define NUMAKER_CLK_CLKSEL3_UART4SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART4SEL_Pos)

Select PLL output as UART4 clock source.

NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART5 clock source.

NUMAKER_CLK_CLKSEL3_UART5SEL_HXT

#define NUMAKER_CLK_CLKSEL3_UART5SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)

Select HXT (external high-speed crystal) as UART5 clock source.

NUMAKER_CLK_CLKSEL3_UART5SEL_LXT

#define NUMAKER_CLK_CLKSEL3_UART5SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)

Select LXT (external low-speed crystal) as UART5 clock source.

NUMAKER_CLK_CLKSEL3_UART5SEL_PLL

#define NUMAKER_CLK_CLKSEL3_UART5SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART5SEL_Pos)

Select PLL output as UART5 clock source.

NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART6 clock source.

NUMAKER_CLK_CLKSEL3_UART6SEL_HXT

#define NUMAKER_CLK_CLKSEL3_UART6SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)

Select HXT (external high-speed crystal) as UART6 clock source.

NUMAKER_CLK_CLKSEL3_UART6SEL_LXT

#define NUMAKER_CLK_CLKSEL3_UART6SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)

Select LXT (external low-speed crystal) as UART6 clock source.

NUMAKER_CLK_CLKSEL3_UART6SEL_PLL

#define NUMAKER_CLK_CLKSEL3_UART6SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART6SEL_Pos)

Select PLL output as UART6 clock source.

NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC

#define NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC   (0x3UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)

Select HIRC (internal high-speed RC oscillator) as UART7 clock source.

NUMAKER_CLK_CLKSEL3_UART7SEL_HXT

#define NUMAKER_CLK_CLKSEL3_UART7SEL_HXT   (0x0UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)

Select HXT (external high-speed crystal) as UART7 clock source.

NUMAKER_CLK_CLKSEL3_UART7SEL_LXT

#define NUMAKER_CLK_CLKSEL3_UART7SEL_LXT   (0x2UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)

Select LXT (external low-speed crystal) as UART7 clock source.

NUMAKER_CLK_CLKSEL3_UART7SEL_PLL

#define NUMAKER_CLK_CLKSEL3_UART7SEL_PLL   (0x1UL << NUMAKER_CLK_CLKSEL3_UART7SEL_Pos)

Select PLL output as UART7 clock source.

NUMAKER_CLK_PCLKDIV_APB0DIV_DIV1

#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set APB0 clock to HCLK/1.

NUMAKER_CLK_PCLKDIV_APB0DIV_DIV16

#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set APB0 clock to HCLK/16.

NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2

#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set APB0 clock to HCLK/2.

NUMAKER_CLK_PCLKDIV_APB0DIV_DIV4

#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set APB0 clock to HCLK/4.

NUMAKER_CLK_PCLKDIV_APB0DIV_DIV8

#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set APB0 clock to HCLK/8.

NUMAKER_CLK_PCLKDIV_APB1DIV_DIV1

#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set APB1 clock to HCLK/1.

NUMAKER_CLK_PCLKDIV_APB1DIV_DIV16

#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set APB1 clock to HCLK/16.

NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2

#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set APB1 clock to HCLK/2.

NUMAKER_CLK_PCLKDIV_APB1DIV_DIV4

#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set APB1 clock to HCLK/4.

NUMAKER_CLK_PCLKDIV_APB1DIV_DIV8

#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set APB1 clock to HCLK/8.

NUMAKER_CLK_PCLKDIV_PCLK0DIV1

#define NUMAKER_CLK_PCLKDIV_PCLK0DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set PCLK0 to HCLK/1.

NUMAKER_CLK_PCLKDIV_PCLK0DIV16

#define NUMAKER_CLK_PCLKDIV_PCLK0DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set PCLK0 to HCLK/16.

NUMAKER_CLK_PCLKDIV_PCLK0DIV2

#define NUMAKER_CLK_PCLKDIV_PCLK0DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set PCLK0 to HCLK/2.

NUMAKER_CLK_PCLKDIV_PCLK0DIV4

#define NUMAKER_CLK_PCLKDIV_PCLK0DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set PCLK0 to HCLK/4.

NUMAKER_CLK_PCLKDIV_PCLK0DIV8

#define NUMAKER_CLK_PCLKDIV_PCLK0DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB0DIV_Pos)

Set PCLK0 to HCLK/8.

NUMAKER_CLK_PCLKDIV_PCLK1DIV1

#define NUMAKER_CLK_PCLKDIV_PCLK1DIV1   (0x0UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set PCLK1 to HCLK/1.

NUMAKER_CLK_PCLKDIV_PCLK1DIV16

#define NUMAKER_CLK_PCLKDIV_PCLK1DIV16   (0x4UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set PCLK1 to HCLK/16.

NUMAKER_CLK_PCLKDIV_PCLK1DIV2

#define NUMAKER_CLK_PCLKDIV_PCLK1DIV2   (0x1UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set PCLK1 to HCLK/2.

NUMAKER_CLK_PCLKDIV_PCLK1DIV4

#define NUMAKER_CLK_PCLKDIV_PCLK1DIV4   (0x2UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set PCLK1 to HCLK/4.

NUMAKER_CLK_PCLKDIV_PCLK1DIV8

#define NUMAKER_CLK_PCLKDIV_PCLK1DIV8   (0x3UL << NUMAKER_CLK_PCLKDIV_APB1DIV_Pos)

Set PCLK1 to HCLK/8.

NUMAKER_CLK_PMUCTL_PDMSEL_DPD

#define NUMAKER_CLK_PMUCTL_PDMSEL_DPD   0x00000006

Deep power-down mode.

NUMAKER_CLK_PMUCTL_PDMSEL_FWPD

#define NUMAKER_CLK_PMUCTL_PDMSEL_FWPD   0x00000002

Fast wake-up power-down mode.

NUMAKER_CLK_PMUCTL_PDMSEL_LLPD

#define NUMAKER_CLK_PMUCTL_PDMSEL_LLPD   0x00000001

Low leakage power-down mode.

NUMAKER_CLK_PMUCTL_PDMSEL_PD

#define NUMAKER_CLK_PMUCTL_PDMSEL_PD   0x00000000

Normal power-down mode.

NUMAKER_CLK_PMUCTL_PDMSEL_SPD

#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD   0x00000004

Standby power-down mode.

NUMAKER_CLKO_MODULE

#define NUMAKER_CLKO_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x3UL << 25) | (28UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (6UL << 0))

Clock frequency output module clock configuration.

NUMAKER_CRC_MODULE

#define NUMAKER_CRC_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (7UL << 0))

CRC generator module clock configuration.

NUMAKER_CRPT_MODULE

#define NUMAKER_CRPT_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (12UL << 0))

Cryptographic accelerator module clock configuration.

NUMAKER_DAC_MODULE

#define NUMAKER_DAC_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (12UL << 0))

DAC module clock configuration.

NUMAKER_EADC1_MODULE

#define NUMAKER_EADC1_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (2UL << 18) | (0xFFUL << 10) | (24UL << 5) | (31UL << 0))

Enhanced ADC 1 module clock configuration.

NUMAKER_EADC_MODULE

#define NUMAKER_EADC_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (0UL << 18) | (0xFFUL << 10) | (16UL << 5) | (28UL << 0))

Enhanced ADC 0 module clock configuration.

NUMAKER_EBI_MODULE

#define NUMAKER_EBI_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (3UL << 0))

External bus interface module clock configuration.

NUMAKER_ECAP0_MODULE

#define NUMAKER_ECAP0_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (26UL << 0))

Enhanced input capture 0 module clock configuration.

NUMAKER_ECAP1_MODULE

#define NUMAKER_ECAP1_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (27UL << 0))

Enhanced input capture 1 module clock configuration.

NUMAKER_EMAC_MODULE

#define NUMAKER_EMAC_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (2UL << 18) | (0xFFUL << 10) | (16UL << 5) | (5UL << 0))

Ethernet MAC controller module clock configuration.

NUMAKER_EPWM0_MODULE

#define NUMAKER_EPWM0_MODULE

Value:

((2UL << 30) | (2UL << 28) | (0x1UL << 25) | (0UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (16UL << 0))

EPWM0 module clock configuration.

NUMAKER_EPWM1_MODULE

#define NUMAKER_EPWM1_MODULE

Value:

((2UL << 30) | (2UL << 28) | (0x1UL << 25) | (1UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (17UL << 0))

EPWM1 module clock configuration.

NUMAKER_FMCIDLE_MODULE

#define NUMAKER_FMCIDLE_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (15UL << 0))

Flash memory controller idle module clock configuration.

NUMAKER_HSOTG_MODULE

#define NUMAKER_HSOTG_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (30UL << 0))

High-speed USB OTG module clock configuration.

NUMAKER_HSUSBD_MODULE

#define NUMAKER_HSUSBD_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (10UL << 0))

High-speed USB device controller module clock configuration.

NUMAKER_I2C0_MODULE

#define NUMAKER_I2C0_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (8UL << 0))

I2C0 module clock configuration.

NUMAKER_I2C1_MODULE

#define NUMAKER_I2C1_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (9UL << 0))

I2C1 module clock configuration.

NUMAKER_I2C2_MODULE

#define NUMAKER_I2C2_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (10UL << 0))

I2C2 module clock configuration.

NUMAKER_I2S0_MODULE

#define NUMAKER_I2S0_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x3UL << 25) | (16UL << 20) | (2UL << 18) | (0xFUL << 10) |  \
 (0UL << 5) | (29UL << 0))

I2S0 audio interface module clock configuration.

NUMAKER_ISP_MODULE

#define NUMAKER_ISP_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (2UL << 0))

Flash ISP controller module clock configuration.

NUMAKER_OPA_MODULE

#define NUMAKER_OPA_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (30UL << 0))

Operational amplifier module clock configuration.

NUMAKER_OTG_MODULE

#define NUMAKER_OTG_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (26UL << 0))

USB OTG module clock configuration.

NUMAKER_PDMA_MODULE

#define NUMAKER_PDMA_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (1UL << 0))

PDMA controller module clock configuration.

NUMAKER_QEI0_MODULE

#define NUMAKER_QEI0_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (22UL << 0))

Quadrature encoder 0 module clock configuration.

NUMAKER_QEI1_MODULE

#define NUMAKER_QEI1_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (23UL << 0))

Quadrature encoder 1 module clock configuration.

NUMAKER_QSPI0_MODULE

#define NUMAKER_QSPI0_MODULE

Value:

((1UL << 30) | (2UL << 28) | (0x3UL << 25) | (2UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (12UL << 0))

QSPI0 module clock configuration.

NUMAKER_QSPI1_MODULE

#define NUMAKER_QSPI1_MODULE

Value:

((2UL << 30) | (3UL << 28) | (0x3UL << 25) | (12UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (4UL << 0))

QSPI1 module clock configuration.

NUMAKER_RTC_MODULE

#define NUMAKER_RTC_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x1UL << 25) | (8UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (1UL << 0))

Real-time clock module clock configuration.

NUMAKER_SC0_MODULE

#define NUMAKER_SC0_MODULE

Value:

((2UL << 30) | (3UL << 28) | (0x3UL << 25) | (0UL << 20) | (1UL << 18) | (0xFFUL << 10) |  \
 (0UL << 5) | (0UL << 0))

Smart card 0 interface module clock configuration.

NUMAKER_SC1_MODULE

#define NUMAKER_SC1_MODULE

Value:

((2UL << 30) | (3UL << 28) | (0x3UL << 25) | (2UL << 20) | (1UL << 18) | (0xFFUL << 10) |  \
 (8UL << 5) | (1UL << 0))

Smart card 1 interface module clock configuration.

NUMAKER_SC2_MODULE

#define NUMAKER_SC2_MODULE

Value:

((2UL << 30) | (3UL << 28) | (0x3UL << 25) | (4UL << 20) | (1UL << 18) | (0xFFUL << 10) |  \
 (16UL << 5) | (2UL << 0))

Smart card 2 interface module clock configuration.

NUMAKER_SDH0_MODULE

#define NUMAKER_SDH0_MODULE

Value:

((0UL << 30) | (0UL << 28) | (0x3UL << 25) | (20UL << 20) | (0UL << 18) | (0xFFUL << 10) | \
 (24UL << 5) | (6UL << 0))

SD host 0 controller module clock configuration.

NUMAKER_SDH1_MODULE

#define NUMAKER_SDH1_MODULE

Value:

((0UL << 30) | (0UL << 28) | (0x3UL << 25) | (22UL << 20) | (2UL << 18) | (0xFFUL << 10) | \
 (24UL << 5) | (17UL << 0))

SD host 1 controller module clock configuration.

NUMAKER_SEN_MODULE

#define NUMAKER_SEN_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (9UL << 0))

Sensor interface module clock configuration.

NUMAKER_SPI0_MODULE

#define NUMAKER_SPI0_MODULE

Value:

((1UL << 30) | (2UL << 28) | (0x3UL << 25) | (4UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (13UL << 0))

SPI0 module clock configuration.

NUMAKER_SPI1_MODULE

#define NUMAKER_SPI1_MODULE

Value:

((1UL << 30) | (2UL << 28) | (0x3UL << 25) | (6UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (14UL << 0))

SPI1 module clock configuration.

NUMAKER_SPI2_MODULE

#define NUMAKER_SPI2_MODULE

Value:

((1UL << 30) | (2UL << 28) | (0x3UL << 25) | (10UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (15UL << 0))

SPI2 module clock configuration.

NUMAKER_SPI3_MODULE

#define NUMAKER_SPI3_MODULE

Value:

((2UL << 30) | (2UL << 28) | (0x3UL << 25) | (12UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (6UL << 0))

SPI3 module clock configuration.

NUMAKER_SPIM_MODULE

#define NUMAKER_SPIM_MODULE

Value:

((0UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (14UL << 0))

SPI flash memory controller module clock configuration.

NUMAKER_TMR0_MODULE

#define NUMAKER_TMR0_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x7UL << 25) | (8UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (2UL << 0))

Timer 0 module clock configuration.

NUMAKER_TMR1_MODULE

#define NUMAKER_TMR1_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x7UL << 25) | (12UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (3UL << 0))

Timer 1 module clock configuration.

NUMAKER_TMR2_MODULE

#define NUMAKER_TMR2_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x7UL << 25) | (16UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (4UL << 0))

Timer 2 module clock configuration.

NUMAKER_TMR3_MODULE

#define NUMAKER_TMR3_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x7UL << 25) | (20UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (5UL << 0))

Timer 3 module clock configuration.

NUMAKER_TRNG_MODULE

#define NUMAKER_TRNG_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (25UL << 0))

True random number generator module clock configuration.

NUMAKER_UART0_MODULE

#define NUMAKER_UART0_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x3UL << 25) | (24UL << 20) | (0UL << 18) | (0xFUL << 10) |  \
 (8UL << 5) | (16UL << 0))

UART0 module clock configuration.

NUMAKER_UART1_MODULE

#define NUMAKER_UART1_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x3UL << 25) | (26UL << 20) | (0UL << 18) | (0xFUL << 10) |  \
 (12UL << 5) | (17UL << 0))

UART1 module clock configuration.

NUMAKER_UART2_MODULE

#define NUMAKER_UART2_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x3UL << 25) | (24UL << 20) | (3UL << 18) | (0xFUL << 10) |  \
 (0UL << 5) | (18UL << 0))

UART2 module clock configuration.

NUMAKER_UART3_MODULE

#define NUMAKER_UART3_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x3UL << 25) | (26UL << 20) | (3UL << 18) | (0xFUL << 10) |  \
 (4UL << 5) | (19UL << 0))

UART3 module clock configuration.

NUMAKER_UART4_MODULE

#define NUMAKER_UART4_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x3UL << 25) | (28UL << 20) | (3UL << 18) | (0xFUL << 10) |  \
 (8UL << 5) | (20UL << 0))

UART4 module clock configuration.

NUMAKER_UART5_MODULE

#define NUMAKER_UART5_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x3UL << 25) | (30UL << 20) | (3UL << 18) | (0xFUL << 10) |  \
 (12UL << 5) | (21UL << 0))

UART5 module clock configuration.

NUMAKER_UART6_MODULE

#define NUMAKER_UART6_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x3UL << 25) | (20UL << 20) | (3UL << 18) | (0xFUL << 10) |  \
 (16UL << 5) | (22UL << 0))

UART6 module clock configuration.

NUMAKER_UART7_MODULE

#define NUMAKER_UART7_MODULE

Value:

((1UL << 30) | (3UL << 28) | (0x3UL << 25) | (22UL << 20) | (3UL << 18) | (0xFUL << 10) |  \
 (20UL << 5) | (23UL << 0))

UART7 module clock configuration.

NUMAKER_USBD_MODULE

#define NUMAKER_USBD_MODULE

Value:

((1UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (1UL << 25) | (8UL << 20) |                  \
 (NUMAKER_MODULE_NoMsk << 18) | (0xFUL << 10) | (4UL << 5) | (27UL << 0))

USB device controller module clock configuration.

NUMAKER_USBH_MODULE

#define NUMAKER_USBH_MODULE

Value:

((0UL << 30) | (0UL << 28) | (0x1UL << 25) | (8UL << 20) | (0UL << 18) | (0xFUL << 10) |   \
 (4UL << 5) | (16UL << 0))

USB host controller module clock configuration.

NUMAKER_USCI0_MODULE

#define NUMAKER_USCI0_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (8UL << 0))

USCI0 module clock configuration.

NUMAKER_USCI1_MODULE

#define NUMAKER_USCI1_MODULE

Value:

((2UL << 30) | (NUMAKER_MODULE_NoMsk << 28) | (NUMAKER_MODULE_NoMsk << 25) |               \
 (NUMAKER_MODULE_NoMsk << 20) | (NUMAKER_MODULE_NoMsk << 18) |                             \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (9UL << 0))

USCI1 module clock configuration.

NUMAKER_WDT_MODULE

#define NUMAKER_WDT_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x3UL << 25) | (0UL << 20) | (NUMAKER_MODULE_NoMsk << 18) |  \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (0UL << 0))

Watchdog timer module clock configuration.

NUMAKER_WWDT_MODULE

#define NUMAKER_WWDT_MODULE

Value:

((1UL << 30) | (1UL << 28) | (0x3UL << 25) | (30UL << 20) | (NUMAKER_MODULE_NoMsk << 18) | \
 (NUMAKER_MODULE_NoMsk << 10) | (NUMAKER_MODULE_NoMsk << 5) | (0UL << 0))

Window watchdog timer module clock configuration.