pinctrl-rza-common.h File Reference

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Macros
#define	PORT_00   0x0000 /* IO port 0 */
#define	PORT_01   0x0100 /* IO port 1 */
#define	PORT_02   0x0200 /* IO port 2 */
#define	PORT_03   0x0300 /* IO port 3 */
#define	PORT_04   0x0400 /* IO port 4 */
#define	PORT_05   0x0500 /* IO port 5 */
#define	PORT_06   0x0600 /* IO port 6 */
#define	PORT_07   0x0700 /* IO port 7 */
#define	PORT_08   0x0800 /* IO port 8 */
#define	PORT_09   0x0900 /* IO port 9 */
#define	PORT_10   0x0A00 /* IO port 10 */
#define	PORT_11   0x0B00 /* IO port 11 */
#define	PORT_12   0x0C00 /* IO port 12 */
#define	PORT_13   0x0D00 /* IO port 13 */
#define	PORT_14   0x0E00 /* IO port 14 */
#define	PORT_15   0x0F00 /* IO port 15 */
#define	PORT_16   0x1000 /* IO port 16 */
#define	PORT_17   0x1100 /* IO port 17 */
#define	PORT_18   0x1200 /* IO port 18 */
#define	RZA_PINMUX(port, pin, func)
#define	BSP_IO_NMI   0xFFFF0100 /* NMI */
#define	BSP_IO_TMS_SWDIO   0xFFFF0200 /* TMS_SWDIO */
#define	BSP_IO_TDO   0xFFFF0300 /* TDO */
#define	BSP_IO_AUDIO_CLK1   0xFFFF0400 /* AUDIO_CLK1 */
#define	BSP_IO_AUDIO_CLK2   0xFFFF0401 /* AUDIO_CLK2 */
#define	BSP_IO_SD0_CLK   0xFFFF0600 /* CD0_CLK */
#define	BSP_IO_SD0_CMD   0xFFFF0601 /* CD0_CMD */
#define	BSP_IO_SD0_RST_N   0xFFFF0602 /* CD0_RST_N */
#define	BSP_IO_SD0_DATA0   0xFFFF0700 /* SD0_DATA0 */
#define	BSP_IO_SD0_DATA1   0xFFFF0701 /* SD0_DATA1 */
#define	BSP_IO_SD0_DATA2   0xFFFF0702 /* SD0_DATA2 */
#define	BSP_IO_SD0_DATA3   0xFFFF0703 /* SD0_DATA3 */
#define	BSP_IO_SD0_DATA4   0xFFFF0704 /* SD0_DATA4 */
#define	BSP_IO_SD0_DATA5   0xFFFF0705 /* SD0_DATA5 */
#define	BSP_IO_SD0_DATA6   0xFFFF0706 /* SD0_DATA6 */
#define	BSP_IO_SD0_DATA7   0xFFFF0707 /* SD0_DATA7 */
#define	BSP_IO_SD1_CLK   0xFFFF0800 /* SD1_CLK */
#define	BSP_IO_SD1_CMD   0xFFFF0801 /* SD1_CMD */
#define	BSP_IO_SD1_DATA0   0xFFFF0900 /* SD1_DATA0 */
#define	BSP_IO_SD1_DATA1   0xFFFF0901 /* SD1_DATA1 */
#define	BSP_IO_SD1_DATA2   0xFFFF0902 /* SD1_DATA2 */
#define	BSP_IO_SD1_DATA3   0xFFFF0903 /* SD1_DATA3 */
#define	BSP_IO_QSPI0_SPCLK   0xFFFF0A00 /* QSPI0_SPCLK */
#define	BSP_IO_QSPI0_IO0   0xFFFF0A01 /* QSPI0_IO0 */
#define	BSP_IO_QSPI0_IO1   0xFFFF0A02 /* QSPI0_IO1 */
#define	BSP_IO_QSPI0_IO2   0xFFFF0A03 /* QSPI0_IO2 */
#define	BSP_IO_QSPI0_IO3   0xFFFF0A04 /* QSPI0_IO3 */
#define	BSP_IO_QSPI0_SSL   0xFFFF0A05 /* QSPI0_SSL */
#define	BSP_IO_OM_CS1_N   0xFFFF0B00 /* OM_CS1_N */
#define	BSP_IO_OM_DQS   0xFFFF0B01 /* OM_DQS */
#define	BSP_IO_OM_SIO4   0xFFFF0B02 /* OM_SIO4 */
#define	BSP_IO_OM_SIO5   0xFFFF0B03 /* OM_SIO5 */
#define	BSP_IO_OM_SIO6   0xFFFF0B04 /* OM_SIO6 */
#define	BSP_IO_OM_SIO7   0xFFFF0B05 /* OM_SIO7 */
#define	BSP_IO_QSPI_RESET_N   0xFFFF0C00 /* QSPI_RESET_N */
#define	BSP_IO_QSPI_WP_N   0xFFFF0C01 /* QSPI_WP_N */
#define	BSP_IO_WDTOVF_PERROUT_N   0xFFFF0D00 /* WDTOVF_PERROUT_N */
#define	BSP_IO_RIIC0_SDA   0xFFFF0E00 /* RIIC0_SDA */
#define	BSP_IO_RIIC0_SCL   0xFFFF0E01 /* RIIC0_SCL */
#define	BSP_IO_RIIC1_SDA   0xFFFF0E02 /* RIIC1_SDA */
#define	BSP_IO_RIIC1_SCL   0xFFFF0E03 /* RIIC1_SCL */
#define	RZA_FILNUM_4_STAGE   0
#define	RZA_FILNUM_8_STAGE   1
#define	RZA_FILNUM_12_STAGE   2
#define	RZA_FILNUM_16_STAGE   3
#define	RZA_FILCLKSEL_NOT_DIV   0
#define	RZA_FILCLKSEL_DIV_9000   1
#define	RZA_FILCLKSEL_DIV_18000   2
#define	RZA_FILCLKSEL_DIV_36000   3
#define	RZA_FILTER_SET(filnum, filclksel)

Macro Definition Documentation

BSP_IO_AUDIO_CLK1

#define BSP_IO_AUDIO_CLK1   0xFFFF0400 /* AUDIO_CLK1 */

BSP_IO_AUDIO_CLK2

#define BSP_IO_AUDIO_CLK2   0xFFFF0401 /* AUDIO_CLK2 */

BSP_IO_NMI

#define BSP_IO_NMI   0xFFFF0100 /* NMI */

BSP_IO_OM_CS1_N

#define BSP_IO_OM_CS1_N   0xFFFF0B00 /* OM_CS1_N */

BSP_IO_OM_DQS

#define BSP_IO_OM_DQS   0xFFFF0B01 /* OM_DQS */

BSP_IO_OM_SIO4

#define BSP_IO_OM_SIO4   0xFFFF0B02 /* OM_SIO4 */

BSP_IO_OM_SIO5

#define BSP_IO_OM_SIO5   0xFFFF0B03 /* OM_SIO5 */

BSP_IO_OM_SIO6

#define BSP_IO_OM_SIO6   0xFFFF0B04 /* OM_SIO6 */

BSP_IO_OM_SIO7

#define BSP_IO_OM_SIO7   0xFFFF0B05 /* OM_SIO7 */

BSP_IO_QSPI0_IO0

#define BSP_IO_QSPI0_IO0   0xFFFF0A01 /* QSPI0_IO0 */

BSP_IO_QSPI0_IO1

#define BSP_IO_QSPI0_IO1   0xFFFF0A02 /* QSPI0_IO1 */

BSP_IO_QSPI0_IO2

#define BSP_IO_QSPI0_IO2   0xFFFF0A03 /* QSPI0_IO2 */

BSP_IO_QSPI0_IO3

#define BSP_IO_QSPI0_IO3   0xFFFF0A04 /* QSPI0_IO3 */

BSP_IO_QSPI0_SPCLK

#define BSP_IO_QSPI0_SPCLK   0xFFFF0A00 /* QSPI0_SPCLK */

BSP_IO_QSPI0_SSL

#define BSP_IO_QSPI0_SSL   0xFFFF0A05 /* QSPI0_SSL */

BSP_IO_QSPI_RESET_N

#define BSP_IO_QSPI_RESET_N   0xFFFF0C00 /* QSPI_RESET_N */

BSP_IO_QSPI_WP_N

#define BSP_IO_QSPI_WP_N   0xFFFF0C01 /* QSPI_WP_N */

BSP_IO_RIIC0_SCL

#define BSP_IO_RIIC0_SCL   0xFFFF0E01 /* RIIC0_SCL */

BSP_IO_RIIC0_SDA

#define BSP_IO_RIIC0_SDA   0xFFFF0E00 /* RIIC0_SDA */

BSP_IO_RIIC1_SCL

#define BSP_IO_RIIC1_SCL   0xFFFF0E03 /* RIIC1_SCL */

BSP_IO_RIIC1_SDA

#define BSP_IO_RIIC1_SDA   0xFFFF0E02 /* RIIC1_SDA */

BSP_IO_SD0_CLK

#define BSP_IO_SD0_CLK   0xFFFF0600 /* CD0_CLK */

BSP_IO_SD0_CMD

#define BSP_IO_SD0_CMD   0xFFFF0601 /* CD0_CMD */

BSP_IO_SD0_DATA0

#define BSP_IO_SD0_DATA0   0xFFFF0700 /* SD0_DATA0 */

BSP_IO_SD0_DATA1

#define BSP_IO_SD0_DATA1   0xFFFF0701 /* SD0_DATA1 */

BSP_IO_SD0_DATA2

#define BSP_IO_SD0_DATA2   0xFFFF0702 /* SD0_DATA2 */

BSP_IO_SD0_DATA3

#define BSP_IO_SD0_DATA3   0xFFFF0703 /* SD0_DATA3 */

BSP_IO_SD0_DATA4

#define BSP_IO_SD0_DATA4   0xFFFF0704 /* SD0_DATA4 */

BSP_IO_SD0_DATA5

#define BSP_IO_SD0_DATA5   0xFFFF0705 /* SD0_DATA5 */

BSP_IO_SD0_DATA6

#define BSP_IO_SD0_DATA6   0xFFFF0706 /* SD0_DATA6 */

BSP_IO_SD0_DATA7

#define BSP_IO_SD0_DATA7   0xFFFF0707 /* SD0_DATA7 */

BSP_IO_SD0_RST_N

#define BSP_IO_SD0_RST_N   0xFFFF0602 /* CD0_RST_N */

BSP_IO_SD1_CLK

#define BSP_IO_SD1_CLK   0xFFFF0800 /* SD1_CLK */

BSP_IO_SD1_CMD

#define BSP_IO_SD1_CMD   0xFFFF0801 /* SD1_CMD */

BSP_IO_SD1_DATA0

#define BSP_IO_SD1_DATA0   0xFFFF0900 /* SD1_DATA0 */

BSP_IO_SD1_DATA1

#define BSP_IO_SD1_DATA1   0xFFFF0901 /* SD1_DATA1 */

BSP_IO_SD1_DATA2

#define BSP_IO_SD1_DATA2   0xFFFF0902 /* SD1_DATA2 */

BSP_IO_SD1_DATA3

#define BSP_IO_SD1_DATA3   0xFFFF0903 /* SD1_DATA3 */

BSP_IO_TDO

#define BSP_IO_TDO   0xFFFF0300 /* TDO */

BSP_IO_TMS_SWDIO

#define BSP_IO_TMS_SWDIO   0xFFFF0200 /* TMS_SWDIO */

BSP_IO_WDTOVF_PERROUT_N

#define BSP_IO_WDTOVF_PERROUT_N   0xFFFF0D00 /* WDTOVF_PERROUT_N */

PORT_00

#define PORT_00   0x0000 /* IO port 0 */

PORT_01

#define PORT_01   0x0100 /* IO port 1 */

PORT_02

#define PORT_02   0x0200 /* IO port 2 */

PORT_03

#define PORT_03   0x0300 /* IO port 3 */

PORT_04

#define PORT_04   0x0400 /* IO port 4 */

PORT_05

#define PORT_05   0x0500 /* IO port 5 */

PORT_06

#define PORT_06   0x0600 /* IO port 6 */

PORT_07

#define PORT_07   0x0700 /* IO port 7 */

PORT_08

#define PORT_08   0x0800 /* IO port 8 */

PORT_09

#define PORT_09   0x0900 /* IO port 9 */

PORT_10

#define PORT_10   0x0A00 /* IO port 10 */

PORT_11

#define PORT_11   0x0B00 /* IO port 11 */

PORT_12

#define PORT_12   0x0C00 /* IO port 12 */

PORT_13

#define PORT_13   0x0D00 /* IO port 13 */

PORT_14

#define PORT_14   0x0E00 /* IO port 14 */

PORT_15

#define PORT_15   0x0F00 /* IO port 15 */

PORT_16

#define PORT_16   0x1000 /* IO port 16 */

PORT_17

#define PORT_17   0x1100 /* IO port 17 */

PORT_18

#define PORT_18   0x1200 /* IO port 18 */

RZA_FILCLKSEL_DIV_18000

#define RZA_FILCLKSEL_DIV_18000   2

RZA_FILCLKSEL_DIV_36000

#define RZA_FILCLKSEL_DIV_36000   3

RZA_FILCLKSEL_DIV_9000

#define RZA_FILCLKSEL_DIV_9000   1

RZA_FILCLKSEL_NOT_DIV

#define RZA_FILCLKSEL_NOT_DIV   0

RZA_FILNUM_12_STAGE

#define RZA_FILNUM_12_STAGE   2

RZA_FILNUM_16_STAGE

#define RZA_FILNUM_16_STAGE   3

RZA_FILNUM_4_STAGE

#define RZA_FILNUM_4_STAGE   0

RZA_FILNUM_8_STAGE

#define RZA_FILNUM_8_STAGE   1

RZA_FILTER_SET

#define RZA_FILTER_SET	(		filnum,
			filclksel )

Value:

(((filnum) & 0x3) << 0x2) | (filclksel & 0x3)

RZA_PINMUX

#define RZA_PINMUX	(		port,
			pin,
			func )

Value:

(port | pin | (func << 4))