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Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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Renesas RX Clock Generator Circuit (CGC) header file. More...
Go to the source code of this file.
Data Structures | |
| struct | clock_control_rx_pclk_cfg |
| Peripheral clock configuration (PCLK). More... | |
| struct | clock_control_rx_subsys_cfg |
| Subsystem clock control configuration. More... | |
| struct | clock_control_rx_pll_cfg |
| PLL configuration structure. More... | |
| struct | clock_control_rx_pll_data |
| PLL control parameters. More... | |
| struct | clock_control_rx_root_cfg |
| Root clock configuration. More... | |
Macros | |
| #define | RX_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) |
| Conditional property getter based on devicetree status. | |
| #define | RX_CGC_CLK_SRC(node_id) |
| Helper to get clock source form device tree. | |
| #define | RX_IF_CLK_SRC(node_id) |
| Helper to get IF clock source form device tree. | |
| #define | RX_LPT_CLK_SRC(node_id) |
| Helper to get LPT clock source form device tree. | |
| #define | RX_CGC_PLL_CLK_SRC(node_id) |
| Helper to get PLL clock source form device tree. | |
Renesas RX Clock Generator Circuit (CGC) header file.