riscv_imsic.h File Reference

#include <zephyr/device.h>
#include <zephyr/types.h>
#include <zephyr/arch/riscv/csr.h>

Go to the source code of this file.

Macros
#define	CSR_MTOPEI   0x35C
#define	CSR_MTOPI   0xFB0
#define	CSR_MISELECT   0x350
#define	CSR_MIREG   0x351
#define	CSR_SETEIPNUM_M   0xFC0 /* Write EIID to set pending bit */
#define	CSR_CLREIPNUM_M   0xFC1 /* Write EIID to clear pending bit */
#define	MTOPEI_EIID_MASK   0x7FF /* Bits [10:0]: External Interrupt ID (0-2047) */
#define	MTOPEI_PRIO_SHIFT   16 /* Bits [23:16]: Priority level */
#define	MTOPEI_PRIO_MASK   (0xFF << MTOPEI_PRIO_SHIFT)
#define	ICSR_EIDELIVERY   0x70
#define	ICSR_EITHRESH   0x72
#define	ICSR_EIP0   0x80
#define	ICSR_EIP1   0x81
#define	ICSR_EIP2   0x82
#define	ICSR_EIP3   0x83
#define	ICSR_EIP4   0x84
#define	ICSR_EIP5   0x85
#define	ICSR_EIP6   0x86
#define	ICSR_EIP7   0x87
#define	ICSR_EIE0   0xC0
#define	ICSR_EIE1   0xC1
#define	ICSR_EIE2   0xC2
#define	ICSR_EIE3   0xC3
#define	ICSR_EIE4   0xC4
#define	ICSR_EIE5   0xC5
#define	ICSR_EIE6   0xC6
#define	ICSR_EIE7   0xC7
#define	EIDELIVERY_ENABLE   BIT(0)
#define	EIDELIVERY_MODE_MMSI   (0U << 29) /* MMSI only: 00 = 0x00000000 */

Functions
uint32_t	riscv_imsic_claim (void)
void	riscv_imsic_enable_eiid (uint32_t eiid)
	Enable an EIID in the CURRENT CPU's IMSIC.
void	riscv_imsic_disable_eiid (uint32_t eiid)
	Disable an EIID in the CURRENT CPU's IMSIC.
int	riscv_imsic_is_enabled (uint32_t eiid)
	Check if an EIID is enabled in the CURRENT CPU's IMSIC.

Macro Definition Documentation

CSR_CLREIPNUM_M

#define CSR_CLREIPNUM_M   0xFC1 /* Write EIID to clear pending bit */

CSR_MIREG

#define CSR_MIREG   0x351

CSR_MISELECT

#define CSR_MISELECT   0x350

CSR_MTOPEI

#define CSR_MTOPEI   0x35C

CSR_MTOPI

#define CSR_MTOPI   0xFB0

CSR_SETEIPNUM_M

#define CSR_SETEIPNUM_M   0xFC0 /* Write EIID to set pending bit */

EIDELIVERY_ENABLE

#define EIDELIVERY_ENABLE   BIT(0)

EIDELIVERY_MODE_MMSI

#define EIDELIVERY_MODE_MMSI   (0U << 29) /* MMSI only: 00 = 0x00000000 */

ICSR_EIDELIVERY

#define ICSR_EIDELIVERY   0x70

ICSR_EIE0

#define ICSR_EIE0   0xC0

ICSR_EIE1

#define ICSR_EIE1   0xC1

ICSR_EIE2

#define ICSR_EIE2   0xC2

ICSR_EIE3

#define ICSR_EIE3   0xC3

ICSR_EIE4

#define ICSR_EIE4   0xC4

ICSR_EIE5

#define ICSR_EIE5   0xC5

ICSR_EIE6

#define ICSR_EIE6   0xC6

ICSR_EIE7

#define ICSR_EIE7   0xC7

ICSR_EIP0

#define ICSR_EIP0   0x80

ICSR_EIP1

#define ICSR_EIP1   0x81

ICSR_EIP2

#define ICSR_EIP2   0x82

ICSR_EIP3

#define ICSR_EIP3   0x83

ICSR_EIP4

#define ICSR_EIP4   0x84

ICSR_EIP5

#define ICSR_EIP5   0x85

ICSR_EIP6

#define ICSR_EIP6   0x86

ICSR_EIP7

#define ICSR_EIP7   0x87

ICSR_EITHRESH

#define ICSR_EITHRESH   0x72

MTOPEI_EIID_MASK

#define MTOPEI_EIID_MASK   0x7FF /* Bits [10:0]: External Interrupt ID (0-2047) */

MTOPEI_PRIO_MASK

#define MTOPEI_PRIO_MASK   (0xFF << MTOPEI_PRIO_SHIFT)

MTOPEI_PRIO_SHIFT

#define MTOPEI_PRIO_SHIFT   16 /* Bits [23:16]: Priority level */

Function Documentation

riscv_imsic_claim()

uint32_t riscv_imsic_claim

(

void

)

riscv_imsic_disable_eiid()

void riscv_imsic_disable_eiid

(

uint32_t

eiid

)

Disable an EIID in the CURRENT CPU's IMSIC.

This function uses CSR instructions that operate on the CPU executing this code. To disable an EIID on a specific hart, this function MUST be called from that hart.

Following PLIC pattern: no parameter validation at API level. Invalid EIIDs are caught in the ISR if they fire.

Parameters

eiid	External Interrupt ID to disable (0-2047)

riscv_imsic_enable_eiid()

void riscv_imsic_enable_eiid

(

uint32_t

eiid

)

Enable an EIID in the CURRENT CPU's IMSIC.

This function uses CSR instructions that operate on the CPU executing this code. To enable an EIID on a specific hart, this function MUST be called from that hart (e.g., using k_thread_cpu_mask_enable).

Following PLIC pattern: no parameter validation at API level. Invalid EIIDs are caught in the ISR if they fire.

Parameters

eiid	External Interrupt ID to enable (0-2047)

riscv_imsic_is_enabled()

int riscv_imsic_is_enabled

(

uint32_t

eiid

)

Check if an EIID is enabled in the CURRENT CPU's IMSIC.

Parameters

eiid	External Interrupt ID to check (0-2047)

Returns

1 if enabled, 0 if disabled