Zephyr API Documentation 4.0.0-rc3
A Scalable Open Source RTOS
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stm32f1_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
8
10
14#define STM32_CLOCK_BUS_AHB1 0x014
15#define STM32_CLOCK_BUS_APB2 0x018
16#define STM32_CLOCK_BUS_APB1 0x01c
17
18#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
19#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
20
22/* defined in stm32_common_clocks.h */
23
25/* Low speed clocks defined in stm32_common_clocks.h */
26#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
27#define STM32_SRC_HSE (STM32_SRC_HSI + 1)
28#define STM32_SRC_PLLCLK (STM32_SRC_HSE + 1)
29
30#define STM32_CLOCK_REG_MASK 0xFFU
31#define STM32_CLOCK_REG_SHIFT 0U
32#define STM32_CLOCK_SHIFT_MASK 0x1FU
33#define STM32_CLOCK_SHIFT_SHIFT 8U
34#define STM32_CLOCK_MASK_MASK 0x7U
35#define STM32_CLOCK_MASK_SHIFT 13U
36#define STM32_CLOCK_VAL_MASK 0x7U
37#define STM32_CLOCK_VAL_SHIFT 16U
38
52#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
53 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
54 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
55 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
56 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
57
59#define CFGR1_REG 0x04
60#define CFGR2_REG 0x2C
61
63#define BDCR_REG 0x20
64
67#define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 17, CFGR2_REG)
68#define I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CFGR2_REG)
70#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
71
73#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
74/* No MCO prescaler support on STM32F1 series. */
75
76#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */