Go to the source code of this file.
◆ BDCR_REG
RCC_BDCR register offset.
◆ CFGR1_REG
RCC_CFGRx register offset.
◆ CFGR2_REG
◆ I2S2_SEL
Value:
#define STM32_DT_CLOCK_SELECT(val, mask, shift, reg)
Pack STM32 source clock selection RCC register bit fields for the DT.
Definition stm32_common_clocks.h:46
#define CFGR2_REG
Definition stm32f1_clock.h:33
Device domain clocks selection helpers.
CFGR2 devices
◆ I2S3_SEL
◆ MCO1_SEL
Value:
#define CFGR1_REG
RCC_CFGRx register offset.
Definition stm32f1_clock.h:32
CFGR1 devices.
◆ RTC_SEL
Value:
#define BDCR_REG
RCC_BDCR register offset.
Definition stm32f1_clock.h:36
BDCR devices.
◆ STM32_CLOCK_BUS_AHB1
#define STM32_CLOCK_BUS_AHB1 0x014 |
Domain clocks.
Bus clocks
◆ STM32_CLOCK_BUS_APB1
#define STM32_CLOCK_BUS_APB1 0x01c |
◆ STM32_CLOCK_BUS_APB2
#define STM32_CLOCK_BUS_APB2 0x018 |
◆ STM32_PERIPH_BUS_MAX
◆ STM32_PERIPH_BUS_MIN
◆ STM32_SRC_EXT_HSE
◆ STM32_SRC_HSE
◆ STM32_SRC_HSI
System clock.
Fixed clocks
◆ STM32_SRC_PLLCLK