syna-sr100-pinctrl.h File Reference

List pinctrl subsystem IDs for Synaptics SR100 family. More...

Go to the source code of this file.

Macros
#define	SRXXX_CTRL_SHIFT   0U
	Pin controller id, bit position, mode, mask and offset of pinmux register, offset of configuration register.
#define	SRXXX_CTRL_MASK   0x07U
	CTRL field mask.
#define	SRXXX_BIT_SHIFT   3U
	BIT field shift.
#define	SRXXX_BIT_MASK   0x1FU
	BIT field mask.
#define	SRXXX_MODE_SHIFT   8U
	MODE field shift.
#define	SRXXX_MODE_MASK   0x07U
	MODE field mask.
#define	SRXXX_MASK_SHIFT   11U
	MASK field shift.
#define	SRXXX_MASK_MASK   0x0FU
	MASK field mask.
#define	SRXXX_REG_SHIFT   16U
	REG field shift.
#define	SRXXX_REG_MASK   0xFFU
	REG field mask.
#define	SRXXX_CFG_SHIFT   24U
	CFG field shift.
#define	SRXXX_CFG_MASK   0xFFU
	CFG field mask.
#define	SRXXX_PINMUX(ctrl, reg, bit, mode, mask, cfg)
	Pin configuration bit field.
#define	SRXXX_GLOBAL_PINMUX(reg, bit, mode, cfg)
	Macros for pinmux selection.
#define	SRXXX_AON_PINMUX(reg, bit, mode, cfg)
	AON.
#define	SRXXX_LPS_PINMUX(reg, bit, mode, cfg)
	LPS.
#define	SRXXX_SWIRE_PINMUX(bit, mode)
	Soundwire.
#define	SRXXX_PORT_PINMUX(reg, bit, mode, mask)
	Macro for port selection.
#define	SRXXX_FIXED_PINMUX(cfg)
	Macro for fixed pinmux.
#define	SRXXX_PINMUX_CTRL(pinmux)
	helpers for register fields
#define	SRXXX_PINMUX_REG(pinmux)
	REG field.
#define	SRXXX_PINMUX_BIT(pinmux)
	BIT field.
#define	SRXXX_PINMUX_MODE(pinmux)
	MODE field.
#define	SRXXX_PINMUX_MASK(pinmux)
	MASK field.
#define	SRXXX_PINMUX_CFG(pinmux)
	CFG field.

Detailed Description

List pinctrl subsystem IDs for Synaptics SR100 family.

Macro Definition Documentation

SRXXX_AON_PINMUX

#define SRXXX_AON_PINMUX	(		reg,
			bit,
			mode,
			cfg )

Value:

SRXXX_PINMUX(1, reg, bit, mode, 7, cfg)

AON.

SRXXX_BIT_MASK

#define SRXXX_BIT_MASK   0x1FU

BIT field mask.

SRXXX_BIT_SHIFT

#define SRXXX_BIT_SHIFT   3U

BIT field shift.

SRXXX_CFG_MASK

#define SRXXX_CFG_MASK   0xFFU

CFG field mask.

SRXXX_CFG_SHIFT

#define SRXXX_CFG_SHIFT   24U

CFG field shift.

SRXXX_CTRL_MASK

#define SRXXX_CTRL_MASK   0x07U

CTRL field mask.

SRXXX_CTRL_SHIFT

#define SRXXX_CTRL_SHIFT   0U

Pin controller id, bit position, mode, mask and offset of pinmux register, offset of configuration register.

CTRL field shift

SRXXX_FIXED_PINMUX

#define SRXXX_FIXED_PINMUX

(

cfg

)

Value:

SRXXX_PINMUX(0, 0, 0, 0, 0, cfg)

Macro for fixed pinmux.

SRXXX_GLOBAL_PINMUX

#define SRXXX_GLOBAL_PINMUX	(		reg,
			bit,
			mode,
			cfg )

Value:

SRXXX_PINMUX(0, reg, bit, mode, 7, cfg)

Macros for pinmux selection.

global

SRXXX_LPS_PINMUX

#define SRXXX_LPS_PINMUX	(		reg,
			bit,
			mode,
			cfg )

Value:

SRXXX_PINMUX(2, reg, bit, mode, 7, cfg)

LPS.

SRXXX_MASK_MASK

#define SRXXX_MASK_MASK   0x0FU

MASK field mask.

SRXXX_MASK_SHIFT

#define SRXXX_MASK_SHIFT   11U

MASK field shift.

SRXXX_MODE_MASK

#define SRXXX_MODE_MASK   0x07U

MODE field mask.

SRXXX_MODE_SHIFT

#define SRXXX_MODE_SHIFT   8U

MODE field shift.

SRXXX_PINMUX

#define SRXXX_PINMUX	(		ctrl,
			reg,
			bit,
			mode,
			mask,
			cfg )

Value:

((((ctrl) & SRXXX_CTRL_MASK) << SRXXX_CTRL_SHIFT) | \
 (((reg)  & SRXXX_REG_MASK)  << SRXXX_REG_SHIFT)  | \
 (((bit)  & SRXXX_BIT_MASK)  << SRXXX_BIT_SHIFT)  | \
 (((mode) & SRXXX_MODE_MASK) << SRXXX_MODE_SHIFT) | \
 (((mask) & SRXXX_MASK_MASK) << SRXXX_MASK_SHIFT) | \
 (((cfg)  & SRXXX_CFG_MASK)  << SRXXX_CFG_SHIFT))

Pin configuration bit field.

Set mask to 0 for fixed pins (XSPI)

Fields:

• ctrl [ 0 : 2 ]
• bit [ 3 : 7 ]
• mode [ 8 : 10 ]
• mask [ 11 : 14 ]
• reg [ 16 : 23 ]
• cfg [ 24 : 31 ]

Parameters

ctrl	Controller (0 = Global, 1 = AON-Main, 2 = LPS_Gear1, 3 = SWIRE)
bit	Bit offset inside register (0..27)
mode	Muxing option (0..7)
mask	Bit mask for muxing option (1..7)
reg	Register offset relative to pinmux base address (0..255)
cfg	Register offset relative to pincfg base address (0..255)

SRXXX_PINMUX_BIT

#define SRXXX_PINMUX_BIT

(

pinmux

)

Value:

(((pinmux) >> SRXXX_BIT_SHIFT) & SRXXX_BIT_MASK)

BIT field.

SRXXX_PINMUX_CFG

#define SRXXX_PINMUX_CFG

(

pinmux

)

Value:

(((pinmux) >> SRXXX_CFG_SHIFT) & SRXXX_CFG_MASK)

CFG field.

SRXXX_PINMUX_CTRL

#define SRXXX_PINMUX_CTRL

(

pinmux

)

Value:

(((pinmux) >> SRXXX_CTRL_SHIFT) & SRXXX_CTRL_MASK)

helpers for register fields

CTRL field

SRXXX_PINMUX_MASK

#define SRXXX_PINMUX_MASK

(

pinmux

)

Value:

(((pinmux) >> SRXXX_MASK_SHIFT) & SRXXX_MASK_MASK)

MASK field.

SRXXX_PINMUX_MODE

#define SRXXX_PINMUX_MODE

(

pinmux

)

Value:

(((pinmux) >> SRXXX_MODE_SHIFT) & SRXXX_MODE_MASK)

MODE field.

SRXXX_PINMUX_REG

#define SRXXX_PINMUX_REG

(

pinmux

)

Value:

(((pinmux) >> SRXXX_REG_SHIFT) & SRXXX_REG_MASK)

REG field.

SRXXX_PORT_PINMUX

#define SRXXX_PORT_PINMUX	(		reg,
			bit,
			mode,
			mask )

Value:

SRXXX_PINMUX(4, reg, bit, mode, mask, 0)

Macro for port selection.

SRXXX_REG_MASK

#define SRXXX_REG_MASK   0xFFU

REG field mask.

SRXXX_REG_SHIFT

#define SRXXX_REG_SHIFT   16U

REG field shift.

SRXXX_SWIRE_PINMUX

#define SRXXX_SWIRE_PINMUX	(		bit,
			mode )

Value:

SRXXX_PINMUX(3, 0, bit, mode, 1, 0)

Soundwire.