syna_sr100_clock.h File Reference

List clock subsystem IDs for Synaptics SR100 family. More...

Go to the source code of this file.

Macros
#define	XSPI_CORE_CLK_CTRL   0x30
	Clock gating helpers.
#define	SD0_CORE_CLK_CTRL   0x38
	clock gating helper for SD0
#define	SD1_CORE_CLK_CTRL   0x3c
	clock gating helper for SD1
#define	SPI_MSTR_SSI_CLK_CTRL   0x40
	clock gating helper for SPI master
#define	SPI_SLV_SSI_CLK_CTRL   0x44
	clock gating helper for SPI slave
#define	I3C0_CORE_CLK_CTRL   0x48
	clock gating helper for I3C0
#define	I3C1_CORE_CLK_CTRL   0x4c
	clock gating helper for I3C1
#define	UART0_CORE_CLK_CTRL   0x50
	clock gating helper for UART0
#define	UART1_CORE_CLK_CTRL   0x54
	clock gating helper for UART1
#define	I2C0_MSTR_CORE_CLK_CTRL   0x58
	clock gating helper for I2C0 master
#define	I2C1_MSTR_CORE_CLK_CTRL   0x5c
	clock gating helper for I2C1 master
#define	I2C_SLV_CORE_CLK_CTRL   0x60
	clock gating helper for I2C slave
#define	USB2_CORE_CLK_CTRL   0x64
	clock gating helper for USB
#define	CGL_REG   16
	Bit locations in GLOBAL_CLK_ENABLE1/2 registers.
#define	AXI_ID   8
	bit shift for AXI clocks
#define	SYNA_IMG_CAM_CLK   0
	Device domain clock selection.
#define	SYNA_GPIO_DB_CLK   1
	GPIO Debounce clock.
#define	SYNA_AXI_CLK   2
	AXI clock.
#define	SYNA_NPU_CLK   3
	NPU clock.
#define	SYNA_DMA0_CLK   4
	DMA0 clock.
#define	SYNA_IMG_SYS_CLK   9
	Image Processing clock (sys).
#define	SYNA_IMG_CFG_CLK   10
	Image Processing clock (cfg).
#define	SYNA_IMG_APB_CLK   11
	Image Processing clock (apb).
#define	SYNA_DMA1_CLK   12
	DMA1 clock.
#define	SYNA_PVT_APB_CLK   13
	Process, Voltage, and Temperature clock.
#define	SYNA_XSPI_CLK   ((XSPI_CORE_CLK_CTRL << CGL_REG) | (7 << AXI_ID) | 32)
	xSPI clock
#define	SYNA_USB_CLK   ((USB2_CORE_CLK_CTRL << CGL_REG) | (8 << AXI_ID) | 35)
	USB clock.
#define	SYNA_SD0_CLK   ((SD0_CORE_CLK_CTRL << CGL_REG) | (5 << AXI_ID) | 33)
	SD0 clock.
#define	SYNA_SD1_CLK   ((SD1_CORE_CLK_CTRL << CGL_REG) | (6 << AXI_ID) | 34)
	SD1 clock.
#define	SYNA_SPI_MSTR_CLK   ((SPI_MSTR_SSI_CLK_CTRL << CGL_REG) | 36)
	SPI master clock.
#define	SYNA_SPI_SLV_CLK   ((SPI_SLV_SSI_CLK_CTRL << CGL_REG) | 37)
	SPI slave clock.
#define	SYNA_I3C0_CLK   ((I3C0_CORE_CLK_CTRL << CGL_REG) | 38)
	I3C0 clock.
#define	SYNA_I3C1_CLK   ((I3C1_CORE_CLK_CTRL << CGL_REG) | 39)
	I3C1 clock.
#define	SYNA_UART0_CLK   ((UART0_CORE_CLK_CTRL << CGL_REG) | 40)
	UART0 clock.
#define	SYNA_UART1_CLK   ((UART1_CORE_CLK_CTRL << CGL_REG) | 41)
	UART1 clock.
#define	SYNA_I2C0_MSTR_CLK   ((I2C0_MSTR_CORE_CLK_CTRL << CGL_REG) | 42)
	I2C0 master clock.
#define	SYNA_I2C1_MSTR_CLK   ((I2C1_MSTR_CORE_CLK_CTRL << CGL_REG) | 43)
	I2C1 master clock.
#define	SYNA_I2C_SLV_CLK   ((I2C_SLV_CORE_CLK_CTRL << CGL_REG) | 44)
	I2C slave clock.
#define	SYNA_GPIO_CFG_CLK   45
	GPIO clock.
#define	SYNA_I2S_CFG_CLK   46
	I2S clock.
#define	SYNA_I2S_TX0_PCLK   47
	I2S TX0 clock.
#define	SYNA_I2S_TX1_PCLK   48
	I2S TX1 clock.
#define	SYNA_I2S_TX2_PCLK   49
	I2S TX2 clock.
#define	SYNA_I2S_TX3_PCLK   50
	I2S TX3 clock.
#define	SYNA_I2S_RX0_PCLK   51
	I2S RX0 clock.
#define	SYNA_I2S_RX1_PCLK   52
	I2S RX1 clock.
#define	SYNA_I2S_RX2_PCLK   53
	I2S RX2 clock.
#define	SYNA_I2S_RX3_PCLK   54
	I2S RX3 clock.
#define	SYNA_I2S_SWIRE_CFG_CLK   55
	I2S SWIRE clock.

Detailed Description

List clock subsystem IDs for Synaptics SR100 family.

Macro Definition Documentation

AXI_ID

#define AXI_ID   8

bit shift for AXI clocks

CGL_REG

#define CGL_REG   16

Bit locations in GLOBAL_CLK_ENABLE1/2 registers.

bit shift for clock gating

I2C0_MSTR_CORE_CLK_CTRL

#define I2C0_MSTR_CORE_CLK_CTRL   0x58

clock gating helper for I2C0 master

I2C1_MSTR_CORE_CLK_CTRL

#define I2C1_MSTR_CORE_CLK_CTRL   0x5c

clock gating helper for I2C1 master

I2C_SLV_CORE_CLK_CTRL

#define I2C_SLV_CORE_CLK_CTRL   0x60

clock gating helper for I2C slave

I3C0_CORE_CLK_CTRL

#define I3C0_CORE_CLK_CTRL   0x48

clock gating helper for I3C0

I3C1_CORE_CLK_CTRL

#define I3C1_CORE_CLK_CTRL   0x4c

clock gating helper for I3C1

SD0_CORE_CLK_CTRL

#define SD0_CORE_CLK_CTRL   0x38

clock gating helper for SD0

SD1_CORE_CLK_CTRL

#define SD1_CORE_CLK_CTRL   0x3c

clock gating helper for SD1

SPI_MSTR_SSI_CLK_CTRL

#define SPI_MSTR_SSI_CLK_CTRL   0x40

clock gating helper for SPI master

SPI_SLV_SSI_CLK_CTRL

#define SPI_SLV_SSI_CLK_CTRL   0x44

clock gating helper for SPI slave

SYNA_AXI_CLK

#define SYNA_AXI_CLK   2

AXI clock.

SYNA_DMA0_CLK

#define SYNA_DMA0_CLK   4

DMA0 clock.

SYNA_DMA1_CLK

#define SYNA_DMA1_CLK   12

DMA1 clock.

SYNA_GPIO_CFG_CLK

#define SYNA_GPIO_CFG_CLK   45

GPIO clock.

SYNA_GPIO_DB_CLK

#define SYNA_GPIO_DB_CLK   1

GPIO Debounce clock.

SYNA_I2C0_MSTR_CLK

#define SYNA_I2C0_MSTR_CLK   ((I2C0_MSTR_CORE_CLK_CTRL << CGL_REG) | 42)

I2C0 master clock.

SYNA_I2C1_MSTR_CLK

#define SYNA_I2C1_MSTR_CLK   ((I2C1_MSTR_CORE_CLK_CTRL << CGL_REG) | 43)

I2C1 master clock.

SYNA_I2C_SLV_CLK

#define SYNA_I2C_SLV_CLK   ((I2C_SLV_CORE_CLK_CTRL << CGL_REG) | 44)

I2C slave clock.

SYNA_I2S_CFG_CLK

#define SYNA_I2S_CFG_CLK   46

I2S clock.

SYNA_I2S_RX0_PCLK

#define SYNA_I2S_RX0_PCLK   51

I2S RX0 clock.

SYNA_I2S_RX1_PCLK

#define SYNA_I2S_RX1_PCLK   52

I2S RX1 clock.

SYNA_I2S_RX2_PCLK

#define SYNA_I2S_RX2_PCLK   53

I2S RX2 clock.

SYNA_I2S_RX3_PCLK

#define SYNA_I2S_RX3_PCLK   54

I2S RX3 clock.

SYNA_I2S_SWIRE_CFG_CLK

#define SYNA_I2S_SWIRE_CFG_CLK   55

I2S SWIRE clock.

SYNA_I2S_TX0_PCLK

#define SYNA_I2S_TX0_PCLK   47

I2S TX0 clock.

SYNA_I2S_TX1_PCLK

#define SYNA_I2S_TX1_PCLK   48

I2S TX1 clock.

SYNA_I2S_TX2_PCLK

#define SYNA_I2S_TX2_PCLK   49

I2S TX2 clock.

SYNA_I2S_TX3_PCLK

#define SYNA_I2S_TX3_PCLK   50

I2S TX3 clock.

SYNA_I3C0_CLK

#define SYNA_I3C0_CLK   ((I3C0_CORE_CLK_CTRL << CGL_REG) | 38)

I3C0 clock.

SYNA_I3C1_CLK

#define SYNA_I3C1_CLK   ((I3C1_CORE_CLK_CTRL << CGL_REG) | 39)

I3C1 clock.

SYNA_IMG_APB_CLK

#define SYNA_IMG_APB_CLK   11

Image Processing clock (apb).

SYNA_IMG_CAM_CLK

#define SYNA_IMG_CAM_CLK   0

Device domain clock selection.

Camera clock

SYNA_IMG_CFG_CLK

#define SYNA_IMG_CFG_CLK   10

Image Processing clock (cfg).

SYNA_IMG_SYS_CLK

#define SYNA_IMG_SYS_CLK   9

Image Processing clock (sys).

SYNA_NPU_CLK

#define SYNA_NPU_CLK   3

NPU clock.

SYNA_PVT_APB_CLK

#define SYNA_PVT_APB_CLK   13

Process, Voltage, and Temperature clock.

SYNA_SD0_CLK

#define SYNA_SD0_CLK   ((SD0_CORE_CLK_CTRL << CGL_REG) | (5 << AXI_ID) | 33)

SD0 clock.

SYNA_SD1_CLK

#define SYNA_SD1_CLK   ((SD1_CORE_CLK_CTRL << CGL_REG) | (6 << AXI_ID) | 34)

SD1 clock.

SYNA_SPI_MSTR_CLK

#define SYNA_SPI_MSTR_CLK   ((SPI_MSTR_SSI_CLK_CTRL << CGL_REG) | 36)

SPI master clock.

SYNA_SPI_SLV_CLK

#define SYNA_SPI_SLV_CLK   ((SPI_SLV_SSI_CLK_CTRL << CGL_REG) | 37)

SPI slave clock.

SYNA_UART0_CLK

#define SYNA_UART0_CLK   ((UART0_CORE_CLK_CTRL << CGL_REG) | 40)

UART0 clock.

SYNA_UART1_CLK

#define SYNA_UART1_CLK   ((UART1_CORE_CLK_CTRL << CGL_REG) | 41)

UART1 clock.

SYNA_USB_CLK

#define SYNA_USB_CLK   ((USB2_CORE_CLK_CTRL << CGL_REG) | (8 << AXI_ID) | 35)

USB clock.

SYNA_XSPI_CLK

#define SYNA_XSPI_CLK   ((XSPI_CORE_CLK_CTRL << CGL_REG) | (7 << AXI_ID) | 32)

xSPI clock

UART0_CORE_CLK_CTRL

#define UART0_CORE_CLK_CTRL   0x50

clock gating helper for UART0

UART1_CORE_CLK_CTRL

#define UART1_CORE_CLK_CTRL   0x54

clock gating helper for UART1

USB2_CORE_CLK_CTRL

#define USB2_CORE_CLK_CTRL   0x64

clock gating helper for USB

XSPI_CORE_CLK_CTRL

#define XSPI_CORE_CLK_CTRL   0x30

Clock gating helpers.

clock gating helper for XSPI