Zephyr API Documentation 4.4.0-rc1
A Scalable Open Source RTOS
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syna_sr100_reset.h File Reference

List reset subsystem IDs for Synaptics SR100 family. More...

Go to the source code of this file.

Macros

#define IMGPROC_RST   0x20
 helpers for RST_REG values
#define NPU_RST   0x30
 NPU reset.
#define DMA0_RST   0x40
 DMA0 reset.
#define DMA1_RST   0x48
 DMA1 reset.
#define AXI_RST   0x50
 AXI reset.
#define APB_PERIF_RST   0x8C
 reset field helper for APB
#define PERIF_RST   0x80
 reset field helper for peripherals
#define TOP_STICKY_RST   0x58
 helpers for STI_REG values
#define PER_STICKY_RST   0x88
 sticky field helper for USB
#define STI_REG   24
 register field helpers
#define STI_MASK   21
 bit mask for sticky field
#define STI_BIT   16
 sticky bit
#define RST_REG   8
 bit shift for reset field
#define RST_MASK   5
 bit mask for reset field
#define RST_BIT   0
 bit shift for reset bit
#define SYNA_IMGPRC_RST   ((TOP_STICKY_RST << STI_REG) | (1 << STI_BIT) | (IMGPROC_RST << RST_REG) | (0 << RST_BIT))
 Device domain reset selection.
#define SYNA_NPU_RST   ((TOP_STICKY_RST << STI_REG) | (0 << STI_BIT) | (NPU_RST << RST_REG) | (0 << RST_BIT))
 NPU reset.
#define SYNA_DMA0_RST   ((TOP_STICKY_RST << STI_REG) | (2 << STI_BIT) | (DMA0_RST << RST_REG) | (0 << RST_BIT))
 DMA0 reset.
#define SYNA_DMA1_RST   ((TOP_STICKY_RST << STI_REG) | (5 << STI_BIT) | (DMA1_RST << RST_REG) | (0 << RST_BIT))
 DMA1 reset.
#define SYNA_AXI_RST   ((AXI_RST << RST_REG) | (0 << RST_BIT))
 AXI reset.
#define SYNA_OTP_RST   ((TOP_STICKY_RST << STI_REG) | (3 << STI_BIT))
 OTP reset.
#define SYNA_CALIB_RST   ((TOP_STICKY_RST << STI_REG) | (6 << STI_BIT))
 Clock Calibration reset.
#define SYNA_USB_RST
 USB reset.
#define SYNA_UART0_RST   ((APB_PERIF_RST << RST_REG) | (0 << RST_BIT))
 UART0 reset.
#define SYNA_UART1_RST   ((APB_PERIF_RST << RST_REG) | (1 << RST_BIT))
 UART1 reset.
#define SYNA_I2C0M_RST   ((APB_PERIF_RST << RST_REG) | (2 << RST_BIT))
 I2C0 master reset.
#define SYNA_I2C1M_RST   ((APB_PERIF_RST << RST_REG) | (3 << RST_BIT))
 I2C1 master reset.
#define SYNA_I2CS_RST   ((APB_PERIF_RST << RST_REG) | (4 << RST_BIT))
 I2C slave reset.
#define SYNA_I3C0_RST   ((APB_PERIF_RST << RST_REG) | (5 << RST_BIT))
 I3C0 reset.
#define SYNA_I3C1_RST   ((APB_PERIF_RST << RST_REG) | (6 << RST_BIT))
 I3C1 reset.
#define SYNA_SPIM_RST   ((APB_PERIF_RST << RST_REG) | (7 << RST_BIT))
 SPI master reset.
#define SYNA_SPIS_RST   ((APB_PERIF_RST << RST_REG) | (8 << RST_BIT))
 SPI slave reset.
#define SYNA_GPIO_RST   ((APB_PERIF_RST << RST_REG) | (9 << RST_BIT))
 GPIO reset.
#define SYNA_SWIRE_RST   ((APB_PERIF_RST << RST_REG) | (19 << RST_BIT))
 Soundwire reset.
#define SYNA_SD0_RST   ((PERIF_RST << RST_REG) | (2 << RST_BIT))
 SD0 reset.
#define SYNA_SD1_RST   ((PERIF_RST << RST_REG) | (3 << RST_BIT))
 SD1 reset.
#define SYNA_XSPI_RST   ((PERIF_RST << RST_REG) | (5 << RST_BIT))
 xSPI reset

Detailed Description

List reset subsystem IDs for Synaptics SR100 family.

Macro Definition Documentation

◆ APB_PERIF_RST

#define APB_PERIF_RST   0x8C

reset field helper for APB

◆ AXI_RST

#define AXI_RST   0x50

AXI reset.

◆ DMA0_RST

#define DMA0_RST   0x40

DMA0 reset.

◆ DMA1_RST

#define DMA1_RST   0x48

DMA1 reset.

◆ IMGPROC_RST

#define IMGPROC_RST   0x20

helpers for RST_REG values

Image Processing reset

◆ NPU_RST

#define NPU_RST   0x30

NPU reset.

◆ PER_STICKY_RST

#define PER_STICKY_RST   0x88

sticky field helper for USB

◆ PERIF_RST

#define PERIF_RST   0x80

reset field helper for peripherals

◆ RST_BIT

#define RST_BIT   0

bit shift for reset bit

◆ RST_MASK

#define RST_MASK   5

bit mask for reset field

◆ RST_REG

#define RST_REG   8

bit shift for reset field

◆ STI_BIT

#define STI_BIT   16

sticky bit

◆ STI_MASK

#define STI_MASK   21

bit mask for sticky field

◆ STI_REG

#define STI_REG   24

register field helpers

bit shift for sticky field

◆ SYNA_AXI_RST

#define SYNA_AXI_RST   ((AXI_RST << RST_REG) | (0 << RST_BIT))

AXI reset.

◆ SYNA_CALIB_RST

#define SYNA_CALIB_RST   ((TOP_STICKY_RST << STI_REG) | (6 << STI_BIT))

Clock Calibration reset.

◆ SYNA_DMA0_RST

#define SYNA_DMA0_RST   ((TOP_STICKY_RST << STI_REG) | (2 << STI_BIT) | (DMA0_RST << RST_REG) | (0 << RST_BIT))

DMA0 reset.

◆ SYNA_DMA1_RST

#define SYNA_DMA1_RST   ((TOP_STICKY_RST << STI_REG) | (5 << STI_BIT) | (DMA1_RST << RST_REG) | (0 << RST_BIT))

DMA1 reset.

◆ SYNA_GPIO_RST

#define SYNA_GPIO_RST   ((APB_PERIF_RST << RST_REG) | (9 << RST_BIT))

GPIO reset.

◆ SYNA_I2C0M_RST

#define SYNA_I2C0M_RST   ((APB_PERIF_RST << RST_REG) | (2 << RST_BIT))

I2C0 master reset.

◆ SYNA_I2C1M_RST

#define SYNA_I2C1M_RST   ((APB_PERIF_RST << RST_REG) | (3 << RST_BIT))

I2C1 master reset.

◆ SYNA_I2CS_RST

#define SYNA_I2CS_RST   ((APB_PERIF_RST << RST_REG) | (4 << RST_BIT))

I2C slave reset.

◆ SYNA_I3C0_RST

#define SYNA_I3C0_RST   ((APB_PERIF_RST << RST_REG) | (5 << RST_BIT))

I3C0 reset.

◆ SYNA_I3C1_RST

#define SYNA_I3C1_RST   ((APB_PERIF_RST << RST_REG) | (6 << RST_BIT))

I3C1 reset.

◆ SYNA_IMGPRC_RST

#define SYNA_IMGPRC_RST   ((TOP_STICKY_RST << STI_REG) | (1 << STI_BIT) | (IMGPROC_RST << RST_REG) | (0 << RST_BIT))

Device domain reset selection.

Image Processing reset

◆ SYNA_NPU_RST

#define SYNA_NPU_RST   ((TOP_STICKY_RST << STI_REG) | (0 << STI_BIT) | (NPU_RST << RST_REG) | (0 << RST_BIT))

NPU reset.

◆ SYNA_OTP_RST

#define SYNA_OTP_RST   ((TOP_STICKY_RST << STI_REG) | (3 << STI_BIT))

OTP reset.

◆ SYNA_SD0_RST

#define SYNA_SD0_RST   ((PERIF_RST << RST_REG) | (2 << RST_BIT))

SD0 reset.

◆ SYNA_SD1_RST

#define SYNA_SD1_RST   ((PERIF_RST << RST_REG) | (3 << RST_BIT))

SD1 reset.

◆ SYNA_SPIM_RST

#define SYNA_SPIM_RST   ((APB_PERIF_RST << RST_REG) | (7 << RST_BIT))

SPI master reset.

◆ SYNA_SPIS_RST

#define SYNA_SPIS_RST   ((APB_PERIF_RST << RST_REG) | (8 << RST_BIT))

SPI slave reset.

◆ SYNA_SWIRE_RST

#define SYNA_SWIRE_RST   ((APB_PERIF_RST << RST_REG) | (19 << RST_BIT))

Soundwire reset.

◆ SYNA_UART0_RST

#define SYNA_UART0_RST   ((APB_PERIF_RST << RST_REG) | (0 << RST_BIT))

UART0 reset.

◆ SYNA_UART1_RST

#define SYNA_UART1_RST   ((APB_PERIF_RST << RST_REG) | (1 << RST_BIT))

UART1 reset.

◆ SYNA_USB_RST

#define SYNA_USB_RST
Value:
((PER_STICKY_RST << STI_REG) | (0 << STI_BIT) | (7 << STI_MASK) | (PERIF_RST << RST_REG) | \
(4 << RST_BIT))
#define STI_MASK
bit mask for sticky field
Definition syna_sr100_reset.h:43
#define STI_BIT
sticky bit
Definition syna_sr100_reset.h:45
#define PERIF_RST
reset field helper for peripherals
Definition syna_sr100_reset.h:31
#define PER_STICKY_RST
sticky field helper for USB
Definition syna_sr100_reset.h:37
#define RST_BIT
bit shift for reset bit
Definition syna_sr100_reset.h:51
#define RST_REG
bit shift for reset field
Definition syna_sr100_reset.h:47
#define STI_REG
register field helpers
Definition syna_sr100_reset.h:41

USB reset.

◆ SYNA_XSPI_RST

#define SYNA_XSPI_RST   ((PERIF_RST << RST_REG) | (5 << RST_BIT))

xSPI reset

◆ TOP_STICKY_RST

#define TOP_STICKY_RST   0x58

helpers for STI_REG values

sticky field helper for peripherals