7#ifndef ZEPHYR_INCLUDE_SYS_BARRIER_H_
8#define ZEPHYR_INCLUDE_SYS_BARRIER_H_
12#if defined(CONFIG_BARRIER_OPERATIONS_ARCH)
13# if defined(CONFIG_ARM)
15# elif defined(CONFIG_ARM64)
18#elif defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
43#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
44 z_barrier_sync_synchronize();
56#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
57 z_barrier_dmem_fence_full();
75#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
76 z_barrier_dsync_fence_full();
94#if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
95 z_barrier_isync_fence_full();
static ALWAYS_INLINE void barrier_sync_synchronize(void)
Full/sequentially-consistent data memory barrier across cores.
Definition barrier.h:41
static ALWAYS_INLINE void barrier_isync_fence_full(void)
Full/sequentially-consistent instruction synchronization barrier.
Definition barrier.h:92
static ALWAYS_INLINE void barrier_dsync_fence_full(void)
Full/sequentially-consistent data synchronization barrier.
Definition barrier.h:73
static ALWAYS_INLINE void barrier_dmem_fence_full(void)
Full/sequentially-consistent data memory barrier.
Definition barrier.h:54