Zephyr API Documentation 4.0.99
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tcpci.h
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1/*
2 * Copyright 2024 Google LLC
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#ifndef ZEPHYR_INCLUDE_USB_C_TCPCI_H_
7#define ZEPHYR_INCLUDE_USB_C_TCPCI_H_
8
20#define TCPC_REG_VENDOR_ID 0x0
21
23#define TCPC_REG_PRODUCT_ID 0x2
24
26#define TCPC_REG_BCD_DEV 0x4
27
29#define TCPC_REG_TC_REV 0x6
31#define TCPC_REG_TC_REV_MAJOR_MASK GENMASK(7, 4)
33#define TCPC_REG_TC_REV_MAJOR(reg) (((reg) & TCPC_REG_TC_REV_MAJOR_MASK) >> 4)
35#define TCPC_REG_TC_REV_MINOR_MASK GENMASK(3, 0)
37#define TCPC_REG_TC_REV_MINOR(reg) ((reg) & TCPC_REG_TC_REV_MINOR_MASK)
38
40#define TCPC_REG_PD_REV 0x8
42#define TCPC_REG_PD_REV_REV_MAJOR_MASK GENMASK(15, 12)
44#define TCPC_REG_PD_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MAJOR_MASK) >> 12)
46#define TCPC_REG_PD_REV_REV_MINOR_MASK GENMASK(11, 8)
48#define TCPC_REG_PD_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MINOR_MASK) >> 8)
50#define TCPC_REG_PD_REV_VER_MAJOR_MASK GENMASK(7, 4)
52#define TCPC_REG_PD_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_VER_MAJOR_MASK) >> 4)
54#define TCPC_REG_PD_REV_VER_MINOR_MASK GENMASK(3, 0)
56#define TCPC_REG_PD_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_REV_VER_VER_MINOR_MASK)
57
59#define TCPC_REG_PD_INT_REV 0xa
61#define TCPC_REG_PD_INT_REV_REV_MAJOR_MASK GENMASK(15, 12)
63#define TCPC_REG_PD_INT_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MAJOR_MASK) >> 12)
65#define TCPC_REG_PD_INT_REV_REV_MINOR_MASK GENMASK(11, 8)
67#define TCPC_REG_PD_INT_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MINOR_MASK) >> 8)
69#define TCPC_REG_PD_INT_REV_VER_MAJOR_MASK GENMASK(7, 4)
71#define TCPC_REG_PD_INT_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_VER_MAJOR_MASK) >> 4)
73#define TCPC_REG_PD_INT_REV_VER_MINOR_MASK GENMASK(3, 0)
75#define TCPC_REG_PD_INT_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_REV_VER_VER_MINOR_MASK)
76
78#define TCPC_REG_ALERT 0x10
80#define TCPC_REG_ALERT_NONE 0x0000
82#define TCPC_REG_ALERT_MASK_ALL 0xffff
84#define TCPC_REG_ALERT_VENDOR_DEF BIT(15)
86#define TCPC_REG_ALERT_ALERT_EXT BIT(14)
88#define TCPC_REG_ALERT_EXT_STATUS BIT(13)
90#define TCPC_REG_ALERT_RX_BEGINNING BIT(12)
92#define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
94#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10)
96#define TCPC_REG_ALERT_FAULT BIT(9)
98#define TCPC_REG_ALERT_V_ALARM_LO BIT(8)
100#define TCPC_REG_ALERT_V_ALARM_HI BIT(7)
102#define TCPC_REG_ALERT_TX_SUCCESS BIT(6)
104#define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
106#define TCPC_REG_ALERT_TX_FAILED BIT(4)
108#define TCPC_REG_ALERT_RX_HARD_RST BIT(3)
110#define TCPC_REG_ALERT_RX_STATUS BIT(2)
112#define TCPC_REG_ALERT_POWER_STATUS BIT(1)
114#define TCPC_REG_ALERT_CC_STATUS BIT(0)
116#define TCPC_REG_ALERT_TX_COMPLETE \
117 (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_TX_FAILED)
118
123#define TCPC_REG_ALERT_MASK 0x12
124
130#define TCPC_REG_POWER_STATUS_MASK 0x14
131
137#define TCPC_REG_FAULT_STATUS_MASK 0x15
138
144#define TCPC_REG_EXT_STATUS_MASK 0x16
145
151#define TCPC_REG_ALERT_EXT_MASK 0x17
152
154#define TCPC_REG_CONFIG_STD_OUTPUT 0x18
156#define TCPC_REG_CONFIG_STD_OUTPUT_HIGH_Z BIT(7)
158#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6)
160#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5)
162#define TCPC_REG_CONFIG_STD_OUTPUT_ACTIVE_CABLE BIT(4)
164#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2)
166#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2)
168#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB (1 << 2)
170#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2)
172#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB_DP (3 << 2)
174#define TCPC_REG_CONFIG_STD_OUTPUT_CONN_PRESENT BIT(1)
176#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
177
179#define TCPC_REG_TCPC_CTRL 0x19
181#define TCPC_REG_TCPC_CTRL_SMBUS_PEC BIT(7)
183#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6)
185#define TCPC_REG_TCPC_CTRL_WATCHDOG_TIMER BIT(5)
187#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4)
189#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_MASK GENMASK(3, 2)
191#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_DISABLED 0
193#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_ALWAYS (2 << 2)
195#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_NO_ALERT (3 << 2)
197#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1)
199#define TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION BIT(0)
200
202#define TCPC_REG_ROLE_CTRL 0x1a
204#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6)
206#define TCPC_REG_ROLE_CTRL_RP_MASK GENMASK(5, 4)
208#define TCPC_REG_ROLE_CTRL_CC2_MASK GENMASK(3, 2)
210#define TCPC_REG_ROLE_CTRL_CC1_MASK GENMASK(1, 0)
212#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \
213 ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \
214 (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \
215 (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK))
216#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
218#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
220#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
222#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)
223
225#define TCPC_REG_FAULT_CTRL 0x1b
227#define TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF BIT(4)
229#define TCPC_REG_FAULT_CTRL_VBUS_DISCHARGE_FAULT BIT(3)
231#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(2)
233#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1)
235#define TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS BIT(0)
236
238#define TCPC_REG_POWER_CTRL 0x1c
240#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7)
242#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6)
244#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5)
246#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4)
248#define TCPC_REG_POWER_CTRL_BLEED_DISCHARGE BIT(3)
250#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2)
257#define TCPC_REG_POWER_CTRL_VCONN_SUPP BIT(1)
259#define TCPC_REG_POWER_CTRL_VCONN_EN BIT(0)
260
262#define TCPC_REG_CC_STATUS 0x1d
264#define TCPC_REG_CC_STATUS_LOOK4CONNECTION BIT(5)
266#define TCPC_REG_CC_STATUS_CONNECT_RESULT BIT(4)
268#define TCPC_REG_CC_STATUS_CC2_STATE_MASK GENMASK(3, 2)
274#define TCPC_REG_CC_STATUS_CC2_STATE(reg) (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
276#define TCPC_REG_CC_STATUS_CC1_STATE_MASK GENMASK(1, 0)
278#define TCPC_REG_CC_STATUS_CC1_STATE(reg) ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)
279
281#define TCPC_REG_POWER_STATUS 0x1e
283#define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7)
285#define TCPC_REG_POWER_STATUS_UNINIT BIT(6)
287#define TCPC_REG_POWER_STATUS_SOURCING_HV BIT(5)
289#define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
291#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3)
296#define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2)
298#define TCPC_REG_POWER_STATUS_VCONN_PRES BIT(1)
300#define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0)
301
303#define TCPC_REG_FAULT_STATUS 0x1f
305#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7)
307#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6)
309#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5)
311#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4)
313#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3)
315#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2)
317#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1)
319#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0)
320
322#define TCPC_REG_EXT_STATUS 0x20
324#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0)
325
327#define TCPC_REG_ALERT_EXT 0x21
329#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2)
331#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1)
333#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0)
334
336#define TCPC_REG_COMMAND 0x23
338#define TCPC_REG_COMMAND_WAKE_I2C 0x11
340#define TCPC_REG_COMMAND_DISABLE_VBUS_DETECT 0x22
342#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33
344#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44
346#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55
348#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66
350#define TCPC_REG_COMMAND_SRC_CTRL_DEF 0x77
352#define TCPC_REG_COMMAND_SRC_CTRL_HV 0x88
354#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99
359#define TCPC_REG_COMMAND_RX_ONE_MORE 0xAA
364#define TCPC_REG_COMMAND_SEND_FRS_SIGNAL 0xCC
366#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD
371#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE
373#define TCPC_REG_COMMAND_I2CIDLE 0xFF
374
376#define TCPC_REG_DEV_CAP_1 0x24
378#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15)
380#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14)
382#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13)
384#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12)
386#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11)
391#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10)
393#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK GENMASK(9, 8)
399#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR(reg) \
400 (((reg) & TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK) >> 8)
402#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF 0
404#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF 1
406#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF 2
408#define TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK GENMASK(7, 5)
409#define TCPC_REG_DEV_CAP_1_POWER_ROLE(reg) \
410 (((reg) & TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK) >> 5)
412#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_OR_SNK 0
414#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC 1
416#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK 2
418#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK_ACC 3
420#define TCPC_REG_DEV_CAP_1_POWER_ROLE_DRP 4
422#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP_ADPT_CBL 5
424#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP 6
426#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4)
428#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3)
430#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2)
435#define TCPC_REG_DEV_CAP_1_SOURCE_HV_VBUS BIT(1)
437#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0)
438
440#define TCPC_REG_DEV_CAP_2 0x26
442#define TCPC_REG_DEV_CAP_2_CAP_3_SUPPORTED BIT(15)
444#define TCPC_REG_DEV_CAP_2_MSG_DISABLE_DISCONNECT BIT(14)
446#define TCPC_REG_DEV_CAP_2_GENERIC_TIMER BIT(13)
453#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12)
455#define TCPC_REG_DEV_CAP_2_SMBUS_PEC BIT(11)
457#define TCPC_REG_DEV_CAP_2_SRC_FRS BIT(10)
459#define TCPC_REG_DEV_CAP_2_SNK_FRS BIT(9)
461#define TCPC_REG_DEV_CAP_2_WATCHDOG_TIMER BIT(8)
467#define TCPC_REG_DEV_CAP_2_SNK_DISC_DET BIT(7)
472#define TCPC_REG_DEV_CAP_2_STOP_DISCHARGE_THRESH BIT(6)
474#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK GENMASK(5, 4)
476#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM(reg) \
477 (((reg) & TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK) >> 4)
479#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_25MV 0
481#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_50MV 1
483#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_100MV 2
485#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK GENMASK(3, 1)
487#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED(reg) \
488 (((reg) & TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK) >> 1)
490#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_0W 0
492#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_5W 1
494#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_2_0W 2
496#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_3_0W 3
498#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_4_0W 4
500#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_5_0W 5
502#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_6_0W 6
504#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_EXTERNAL 7
506#define TCPC_REG_DEV_CAP_2_VCONN_OVC_FAULT BIT(0)
507
509#define TCPC_REG_STD_INPUT_CAP 0x28
511#define TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK GENMASK(4, 3)
513#define TCPC_REG_STD_INPUT_CAP_SRC_FRS(reg) (((reg) & TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK) >> 3)
515#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_NONE 0
517#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_INPUT 1
519#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_BOTH 2
521#define TCPC_REG_STD_INPUT_CAP_EXT_OVP BIT(2)
523#define TCPC_REG_STD_INPUT_CAP_EXT_OCP BIT(1)
525#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0)
526
528#define TCPC_REG_STD_OUTPUT_CAP 0x29
530#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7)
532#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6)
534#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5)
536#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4)
538#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3)
540#define TCPC_REG_STD_OUTPUT_CAP_MUX_CFG_CTRL BIT(2)
542#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1)
544#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0)
545
547#define TCPC_REG_CONFIG_EXT_1 0x2A
553#define TCPC_REG_CONFIG_EXT_1_FRS_SNK_DIR BIT(1)
560#define TCPC_REG_CONFIG_EXT_1_STD_IN_SRC_FRS BIT(0)
561
567#define TCPC_REG_GENERIC_TIMER 0x2c
568
570#define TCPC_REG_MSG_HDR_INFO 0x2e
572#define TCPC_REG_MSG_HDR_INFO_CABLE_PLUG BIT(4)
574#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK BIT(3)
576#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE(reg) (((reg) & TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK) >> 3)
578#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_UFP 0
580#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_DFP 1
582#define TCPC_REG_MSG_HDR_INFO_PD_REV_MASK GENMASK(2, 1)
584#define TCPC_REG_MSG_HDR_INFO_PD_REV(reg) (((reg) & TCPC_REG_MSG_HDR_INFO_PD_REV_MASK) >> 1)
586#define TCPC_REG_MSG_HDR_INFO_PD_REV_1_0 0
588#define TCPC_REG_MSG_HDR_INFO_PD_REV_2_0 1
590#define TCPC_REG_MSG_HDR_INFO_PD_REV_3_0 2
592#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK BIT(0)
594#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE(reg) ((reg) & TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK)
596#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SNK 0
598#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SRC 1
603#define TCPC_REG_MSG_HDR_INFO_SET(pd_rev_type, drole, prole) \
604 ((drole) << 3 | (pd_rev_type << 1) | (prole))
606#define TCPC_REG_MSG_HDR_INFO_ROLES_MASK (TCPC_REG_MSG_HDR_INFO_SET(3, 1, 1))
607
609#define TCPC_REG_RX_DETECT 0x2f
617#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7)
619#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6)
621#define TCPC_REG_RX_DETECT_HRST BIT(5)
623#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4)
625#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3)
627#define TCPC_REG_RX_DETECT_SOPPP BIT(2)
629#define TCPC_REG_RX_DETECT_SOPP BIT(1)
631#define TCPC_REG_RX_DETECT_SOP BIT(0)
633#define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST)
635#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \
636 (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | TCPC_REG_RX_DETECT_SOPPP | \
637 TCPC_REG_RX_DETECT_HRST)
638
645#define TCPC_REG_RX_BUFFER 0x30
646
648#define TCPC_REG_TRANSMIT 0x50
650#define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) ((retries) << 4 | (type))
652#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type)
654#define TCPC_REG_TRANSMIT_TYPE_SOP 0
656#define TCPC_REG_TRANSMIT_TYPE_SOPP 1
658#define TCPC_REG_TRANSMIT_TYPE_SOPPP 2
660#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_P 3
662#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_PP 4
664#define TCPC_REG_TRANSMIT_TYPE_HRST 5
666#define TCPC_REG_TRANSMIT_TYPE_CABLE_RST 6
668#define TCPC_REG_TRANSMIT_TYPE_BIST 7
669
677#define TCPC_REG_TX_BUFFER 0x51
678
680#define TCPC_REG_VBUS_VOLTAGE 0x70
682#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK GENMASK(9, 0)
684#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(reg) ((reg) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK)
686#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK GENMASK(11, 10)
688#define TCPC_REG_VBUS_VOLTAGE_SCALE(reg) \
689 (1 << (((reg) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK) >> 10))
691#define TCPC_REG_VBUS_VOLTAGE_LSB 25
696#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \
697 (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(x) * \
698 TCPC_REG_VBUS_VOLTAGE_LSB)
699
701#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72
708#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_LSB 25
710#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_MASK GENMASK(11, 0)
712#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */
713
715#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74
722#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_LSB 25
724#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_MASK GENMASK(11, 0)
726#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_DEFAULT 0x0020 /* 0.8 V */
727
729#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76
736#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_LSB 25
738#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_MASK GENMASK(11, 0)
739
741#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78
748#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_LSB 25
750#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_MASK GENMASK(11, 0)
751
758#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a
765#define TCPC_REG_VBUS_NONDEFAULT_TARGET_LSB 20
766
768#define TCPC_REG_DEV_CAP_3 0x7c
770#define TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK GENMASK(2, 0)
772#define TCPC_REG_DEV_CAP_3_VBUS_MAX(reg) ((reg) & TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK)
774#define TCPC_REG_DEV_CAP_3_VBUS_MAX_5V 0
776#define TCPC_REG_DEV_CAP_3_VBUS_MAX_9V 1
778#define TCPC_REG_DEV_CAP_3_VBUS_MAX_15V 2
780#define TCPC_REG_DEV_CAP_3_VBUS_MAX_20V 3
782#define TCPC_REG_DEV_CAP_3_VBUS_MAX_28V 4
784#define TCPC_REG_DEV_CAP_3_VBUS_MAX_36V 5
786#define TCPC_REG_DEV_CAP_3_VBUS_MAX_48V 6
787
788#endif /* ZEPHYR_INCLUDE_USB_C_TCPCI_H_ */