tcpci.h File Reference

Registers and fields definitions for TypeC Port Controller Interface. More...

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Macros
#define	TCPC_REG_VENDOR_ID   0x0
	Register address - vendor id.
#define	TCPC_REG_PRODUCT_ID   0x2
	Register address - product id.
#define	TCPC_REG_BCD_DEV   0x4
	Register address - version of TCPC.
#define	TCPC_REG_TC_REV   0x6
	Register address - USB TypeC version.
#define	TCPC_REG_TC_REV_MAJOR_MASK   GENMASK(7, 4)
	Mask for major part of type-c release supported.
#define	TCPC_REG_TC_REV_MAJOR(reg)
	Macro to extract the major part of type-c release supported.
#define	TCPC_REG_TC_REV_MINOR_MASK   GENMASK(3, 0)
	Mask for minor part of type-c release supported.
#define	TCPC_REG_TC_REV_MINOR(reg)
	Macro to extract the minor part of type-c release supported.
#define	TCPC_REG_PD_REV   0x8
	Register address - Power delivery revision.
#define	TCPC_REG_PD_REV_REV_MAJOR_MASK   GENMASK(15, 12)
	Mask for major part of USB PD revision supported.
#define	TCPC_REG_PD_REV_REV_MAJOR(reg)
	Macro to extract the major part of USB PD revision supported.
#define	TCPC_REG_PD_REV_REV_MINOR_MASK   GENMASK(11, 8)
	Mask for minor part of USB PD revision supported.
#define	TCPC_REG_PD_REV_REV_MINOR(reg)
	Macro to extract the minor part of USB PD revision supported.
#define	TCPC_REG_PD_REV_VER_MAJOR_MASK   GENMASK(7, 4)
	Mask for major part of USB PD version supported.
#define	TCPC_REG_PD_REV_VER_MAJOR(reg)
	Macro to extract the major part of USB PD version supported.
#define	TCPC_REG_PD_REV_VER_MINOR_MASK   GENMASK(3, 0)
	Mask for minor part of USB PD version supported.
#define	TCPC_REG_PD_REV_VER_MINOR(reg)
	Macro to extract the minor part of USB PD version supported.
#define	TCPC_REG_PD_INT_REV   0xa
	Register address - interface revision and version.
#define	TCPC_REG_PD_INT_REV_REV_MAJOR_MASK   GENMASK(15, 12)
	Mask for major part of USB Port Controller Interface revision supported.
#define	TCPC_REG_PD_INT_REV_REV_MAJOR(reg)
	Macro to extract the major part of USB Port Controller Interface revision supported.
#define	TCPC_REG_PD_INT_REV_REV_MINOR_MASK   GENMASK(11, 8)
	Mask for minor part of USB Port Controller Interface revision supported.
#define	TCPC_REG_PD_INT_REV_REV_MINOR(reg)
	Macro to extract the minor part of USB Port Controller Interface revision supported.
#define	TCPC_REG_PD_INT_REV_VER_MAJOR_MASK   GENMASK(7, 4)
	Mask for major part of USB Port Controller Interface version supported.
#define	TCPC_REG_PD_INT_REV_VER_MAJOR(reg)
	Macro to extract the major part of USB Port Controller Interface version supported.
#define	TCPC_REG_PD_INT_REV_VER_MINOR_MASK   GENMASK(3, 0)
	Mask for minor part of USB Port Controller Interface version supported.
#define	TCPC_REG_PD_INT_REV_VER_MINOR(reg)
	Macro to extract the minor part of USB Port Controller Interface version supported.
#define	TCPC_REG_ALERT   0x10
	Register address - alert.
#define	TCPC_REG_ALERT_NONE   0x0000
	Value for clear alert.
#define	TCPC_REG_ALERT_MASK_ALL   0xffff
	Value mask for all alert bits.
#define	TCPC_REG_ALERT_VENDOR_DEF   BIT(15)
	Bit for vendor defined alert.
#define	TCPC_REG_ALERT_ALERT_EXT   BIT(14)
	Bit for extended alert.
#define	TCPC_REG_ALERT_EXT_STATUS   BIT(13)
	Bit for extended status alert.
#define	TCPC_REG_ALERT_RX_BEGINNING   BIT(12)
	Bit for beginning of data receive.
#define	TCPC_REG_ALERT_VBUS_DISCNCT   BIT(11)
	Bit for vbus disconnection alert.
#define	TCPC_REG_ALERT_RX_BUF_OVF   BIT(10)
	Bit for receive buffer overflow alert.
#define	TCPC_REG_ALERT_FAULT   BIT(9)
	Bit for fault alert.
#define	TCPC_REG_ALERT_V_ALARM_LO   BIT(8)
	Bit for low vbus alarm.
#define	TCPC_REG_ALERT_V_ALARM_HI   BIT(7)
	Bit for high vbus alarm.
#define	TCPC_REG_ALERT_TX_SUCCESS   BIT(6)
	Bit for transmission success.
#define	TCPC_REG_ALERT_TX_DISCARDED   BIT(5)
	Bit for transmission discard alert.
#define	TCPC_REG_ALERT_TX_FAILED   BIT(4)
	Bit for transmission fail alert.
#define	TCPC_REG_ALERT_RX_HARD_RST   BIT(3)
	Bit for received hard reset alert.
#define	TCPC_REG_ALERT_RX_STATUS   BIT(2)
	Bit for data received alert.
#define	TCPC_REG_ALERT_POWER_STATUS   BIT(1)
	Bit for power status alert.
#define	TCPC_REG_ALERT_CC_STATUS   BIT(0)
	Bit for CC lines status alert.
#define	TCPC_REG_ALERT_TX_COMPLETE    (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_TX_FAILED)
	Bits for any of transmission status alert.
#define	TCPC_REG_ALERT_MASK   0x12
	Register address - alert mask The bits for specific masks are on the same positions as for the.
#define	TCPC_REG_POWER_STATUS_MASK   0x14
	Register address - power status mask The bits for specific masks are on the same positions as for the.
#define	TCPC_REG_FAULT_STATUS_MASK   0x15
	Register address - fault status mask The bits for specific masks are on the same positions as for the.
#define	TCPC_REG_EXT_STATUS_MASK   0x16
	Register address - extended status mask The bits for specific masks are on the same positions as for the.
#define	TCPC_REG_ALERT_EXT_MASK   0x17
	Register address - extended alert mask The bits for specific masks are on the same positions as for the.
#define	TCPC_REG_CONFIG_STD_OUTPUT   0x18
	Register address - configure standard output.
#define	TCPC_REG_CONFIG_STD_OUTPUT_HIGH_Z   BIT(7)
	Bit for high impedance outputs.
#define	TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N   BIT(6)
	Bit for debug accessory connected#.
#define	TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N   BIT(5)
	Bit for audio accessory connected#.
#define	TCPC_REG_CONFIG_STD_OUTPUT_ACTIVE_CABLE   BIT(4)
	Bit for active cable.
#define	TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK   (3 << 2)
	Value mask for mux control.
#define	TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE   (0 << 2)
	Value for mux - no connection.
#define	TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB   (1 << 2)
	Value for mux - USB3.1 connected.
#define	TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP   (2 << 2)
	Value for mux - DP alternate mode with 4 lanes.
#define	TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB_DP   (3 << 2)
	Value for mux - USB3.1 + DP 0&1 lines.
#define	TCPC_REG_CONFIG_STD_OUTPUT_CONN_PRESENT   BIT(1)
	Bit for connection present.
#define	TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED   BIT(0)
	Bit for connector orientation.
#define	TCPC_REG_TCPC_CTRL   0x19
	Register address - TCPC control.
#define	TCPC_REG_TCPC_CTRL_SMBUS_PEC   BIT(7)
	Bit for SMBus PEC enabled.
#define	TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT   BIT(6)
	Bit for enabling the alert assertion when a connection is found.
#define	TCPC_REG_TCPC_CTRL_WATCHDOG_TIMER   BIT(5)
	Bit for watchdog monitoring.
#define	TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL   BIT(4)
	Bit for enable debug accessory control by TCPM.
#define	TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_MASK   GENMASK(3, 2)
	Mask.
#define	TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_DISABLED   0
	Value for clock stretching disabled.
#define	TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_ALWAYS   (2 << 2)
	Value for limited clock stretching enabled.
#define	TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_NO_ALERT   (3 << 2)
	Value for clock stretching enabled only when alert is NOT asserted.
#define	TCPC_REG_TCPC_CTRL_BIST_TEST_MODE   BIT(1)
	Bit for BIST test mode enabled.
#define	TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION   BIT(0)
	Bit for plug orientation and vconn destination.
#define	TCPC_REG_ROLE_CTRL   0x1a
	Register address - role control.
#define	TCPC_REG_ROLE_CTRL_DRP_MASK   BIT(6)
	Bit for dual-role port.
#define	TCPC_REG_ROLE_CTRL_RP_MASK   GENMASK(5, 4)
	Mask to extract the RP value from register value.
#define	TCPC_REG_ROLE_CTRL_CC2_MASK   GENMASK(3, 2)
	Mask to extract the CC2 pull value from register value.
#define	TCPC_REG_ROLE_CTRL_CC1_MASK   GENMASK(1, 0)
	Mask to extract the CC! pull value from register value.
#define	TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2)
	Macro to set the register value from drp, rp and CC lines values.
#define	TCPC_REG_ROLE_CTRL_DRP(reg)
#define	TCPC_REG_ROLE_CTRL_RP(reg)
	Macro to extract the enum tc_rp_value from register value.
#define	TCPC_REG_ROLE_CTRL_CC2(reg)
	Macro to extract the enum tc_cc_pull for CC2 from register value.
#define	TCPC_REG_ROLE_CTRL_CC1(reg)
	Macro to extract the enum tc_cc_pull for CC1 from register value.
#define	TCPC_REG_FAULT_CTRL   0x1b
	Register address - fault control.
#define	TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF   BIT(4)
	Bit for block the standard input signal force off vbus control.
#define	TCPC_REG_FAULT_CTRL_VBUS_DISCHARGE_FAULT   BIT(3)
	Bit for disabling the vbus discharge fault detection timer.
#define	TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS   BIT(2)
	Bit for disabling the vbus over current detection.
#define	TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS   BIT(1)
	Bit for disabling the vbus over voltage detection.
#define	TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS   BIT(0)
	Bit for disabling the vconn over current detection.
#define	TCPC_REG_POWER_CTRL   0x1c
	Register address - power control.
#define	TCPC_REG_POWER_CTRL_FRS_ENABLE   BIT(7)
	Bit for fast role swap enable.
#define	TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS   BIT(6)
	Bit for disabling the vbus voltage monitoring.
#define	TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS   BIT(5)
	Bit for disabling the voltage alarms.
#define	TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT   BIT(4)
	Bit for enabling the automatic vbus discharge based on the vbus voltage.
#define	TCPC_REG_POWER_CTRL_BLEED_DISCHARGE   BIT(3)
	Bit for enabling the bleed discharge of vbus.
#define	TCPC_REG_POWER_CTRL_FORCE_DISCHARGE   BIT(2)
	Bit for enabling the forced vbus discharge.
#define	TCPC_REG_POWER_CTRL_VCONN_SUPP   BIT(1)
	Bit for enabling the vconn power supported.
#define	TCPC_REG_POWER_CTRL_VCONN_EN   BIT(0)
	Bit for enabling the vconn sourcing to CC line.
#define	TCPC_REG_CC_STATUS   0x1d
	Register address - CC lines status.
#define	TCPC_REG_CC_STATUS_LOOK4CONNECTION   BIT(5)
	Bit for active looking for a connection by TCPC, both DRP and sink/source only.
#define	TCPC_REG_CC_STATUS_CONNECT_RESULT   BIT(4)
	Bit for connection result, set if presenting Rd, unset if presenting Rp.
#define	TCPC_REG_CC_STATUS_CC2_STATE_MASK   GENMASK(3, 2)
	Mask for CC2 line state.
#define	TCPC_REG_CC_STATUS_CC2_STATE(reg)
	Macro to extract the status value of CC2 line.
#define	TCPC_REG_CC_STATUS_CC1_STATE_MASK   GENMASK(1, 0)
	Mask for CC1 line state.
#define	TCPC_REG_CC_STATUS_CC1_STATE(reg)
	Macto to extract the status value of CC1 line.
#define	TCPC_REG_POWER_STATUS   0x1e
	Register address - power status.
#define	TCPC_REG_POWER_STATUS_DEBUG_ACC_CON   BIT(7)
	Bit for debug accessory connected.
#define	TCPC_REG_POWER_STATUS_UNINIT   BIT(6)
	Bit for internal initialization in-progress.
#define	TCPC_REG_POWER_STATUS_SOURCING_HV   BIT(5)
	Bit for sourcing high voltage.
#define	TCPC_REG_POWER_STATUS_SOURCING_VBUS   BIT(4)
	Bit for sourcing vbus.
#define	TCPC_REG_POWER_STATUS_VBUS_DET   BIT(3)
	Bit for vbus detection enabled.
#define	TCPC_REG_POWER_STATUS_VBUS_PRES   BIT(2)
	Bit for vbus present.
#define	TCPC_REG_POWER_STATUS_VCONN_PRES   BIT(1)
	Bit for vconn present.
#define	TCPC_REG_POWER_STATUS_SINKING_VBUS   BIT(0)
	Bit for sinking vbus.
#define	TCPC_REG_FAULT_STATUS   0x1f
	Register address - fault status.
#define	TCPC_REG_FAULT_STATUS_ALL_REGS_RESET   BIT(7)
	Bit for all registers reset to default.
#define	TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS   BIT(6)
	Bit for force vbus off due to external fault.
#define	TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL   BIT(5)
	Bit for auto discharge failed.
#define	TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL   BIT(4)
	Bit for force discharge failed.
#define	TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT   BIT(3)
	Bit for internal or external vbus over current.
#define	TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE   BIT(2)
	Bit for internal or external vbus over voltage.
#define	TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT   BIT(1)
	Bit for vconn over current.
#define	TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR   BIT(0)
	Bit for I2C interface error.
#define	TCPC_REG_EXT_STATUS   0x20
	Register address - extended status.
#define	TCPC_REG_EXT_STATUS_SAFE0V   BIT(0)
	Bit for vbus at vSafe0V.
#define	TCPC_REG_ALERT_EXT   0x21
	Register address - alert extended.
#define	TCPC_REG_ALERT_EXT_TIMER_EXPIRED   BIT(2)
	Bit for timer expired.
#define	TCPC_REG_ALERT_EXT_SRC_FRS   BIT(1)
	Bit for source fast role swap.
#define	TCPC_REG_ALERT_EXT_SNK_FRS   BIT(0)
	Bit for sink fast role swap.
#define	TCPC_REG_COMMAND   0x23
	Register address - command.
#define	TCPC_REG_COMMAND_WAKE_I2C   0x11
	Value for wake i2c command.
#define	TCPC_REG_COMMAND_DISABLE_VBUS_DETECT   0x22
	Value for disable vbus detect command - disable vbus present and vSafe0V detection.
#define	TCPC_REG_COMMAND_ENABLE_VBUS_DETECT   0x33
	Value for enable vbus detect command - enable vbus present and vSafe0V detection.
#define	TCPC_REG_COMMAND_SNK_CTRL_LOW   0x44
	Value for disable sink vbus - disable sinking power over vbus.
#define	TCPC_REG_COMMAND_SNK_CTRL_HIGH   0x55
	Value for sink vbus - enable sinking power over vbus and vbus present detection.
#define	TCPC_REG_COMMAND_SRC_CTRL_LOW   0x66
	Value for disable source vbus - disable sourcing power over vbus.
#define	TCPC_REG_COMMAND_SRC_CTRL_DEF   0x77
	Value for source vbus default voltage - enable sourcing vSafe5V over vbus.
#define	TCPC_REG_COMMAND_SRC_CTRL_HV   0x88
	Value for source vbus high voltage - enable sourcing high voltage over vbus.
#define	TCPC_REG_COMMAND_LOOK4CONNECTION   0x99
	Value for look for connection - start DRP toggling if DRP role is set.
#define	TCPC_REG_COMMAND_RX_ONE_MORE   0xAA
	Value for rx one more Configure receiver to automatically clear the receive_detect register after sending next GoodCRC.
#define	TCPC_REG_COMMAND_SEND_FRS_SIGNAL   0xCC
	Value for send fast role swap signal Send FRS if TCPC is source with FRS enabled in power control register.
#define	TCPC_REG_COMMAND_RESET_TRANSMIT_BUF   0xDD
	Value for reset transmit buffer - TCPC resets the pointer of transmit buffer to offset 1.
#define	TCPC_REG_COMMAND_RESET_RECEIVE_BUF   0xEE
	Value for reset receive buffer If buffer pointer is at 132 or less, it is reset to 1, otherwise it is reset to 133.
#define	TCPC_REG_COMMAND_I2CIDLE   0xFF
	Value for i2c idle.
#define	TCPC_REG_DEV_CAP_1   0x24
	Register address - device capabilities 1.
#define	TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET   BIT(15)
	Bit for vbus high voltage target - if set, VBUS_HV_TARGET register is implemented.
#define	TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING   BIT(14)
	Bit for vbus over current reporting - if set, vbus over current is reported by TCPC.
#define	TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING   BIT(13)
	Bit for vbus over voltage reporting - if set, vbus over voltage is reported by TCPC.
#define	TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE   BIT(12)
	Bit for bleed discharge - if set, bleed discharge is implemented in TCPC.
#define	TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE   BIT(11)
	Bit for force discharge - if set, force discharge is implemented in TCPC.
#define	TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE   BIT(10)
	Bit for vbus measurement and alarm capable If set, TCPC supports vbus voltage measurement and vbus voltage alarms.
#define	TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK   GENMASK(9, 8)
	Mask for source resistor supported.
#define	TCPC_REG_DEV_CAP_1_SRC_RESISTOR(reg)
	Macro to extract the supported source resistors from register value The value can be cast to enum tc_rp_value and value can be treated as highest amperage supported since the TCPC has also to support lower values than specified.
#define	TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF   0
	Value for Rp default only - only default amperage is supported.
#define	TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF   1
	Value for Rp 1.5A and default - support for 1.5A and for default amperage.
#define	TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF   2
	Value for Rp 3.0A, 1.5A and default - support for 3.0A, 1.5A and default amperage.
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK   GENMASK(7, 5)
	Mask for power roles supported.
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE(reg)
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_OR_SNK   0
	Value for support both source and sink only (no DRP)
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC   1
	Value for support source role only.
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK   2
	Value for support sink role only.
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK_ACC   3
	Value for support sink role with accessory.
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_DRP   4
	Value for support dual-role port only.
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP_ADPT_CBL   5
	Value for support source, sink, dual-role port, adapter and cable.
#define	TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP   6
	Value for support source, sink and dual-role port.
#define	TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED   BIT(4)
	Bit for debug SOP' and SOP'' support - if set, all SOP* messages are supported.
#define	TCPC_REG_DEV_CAP_1_SOURCE_VCONN   BIT(3)
	Bit for source vconn - if set, TCPC is capable of switching the vconn source.
#define	TCPC_REG_DEV_CAP_1_SINK_VBUS   BIT(2)
	Bit for sink vbus - if set, TCPC is capable of controling the sink path to the system load.
#define	TCPC_REG_DEV_CAP_1_SOURCE_HV_VBUS   BIT(1)
	Bit for source high voltage vbus.
#define	TCPC_REG_DEV_CAP_1_SOURCE_VBUS   BIT(0)
	Bit for source vbus - if set, TCPC is capable of controlling the source path to vbus.
#define	TCPC_REG_DEV_CAP_2   0x26
	Register address - device capabilities 2.
#define	TCPC_REG_DEV_CAP_2_CAP_3_SUPPORTED   BIT(15)
	Bit for device capabilities 3 support.
#define	TCPC_REG_DEV_CAP_2_MSG_DISABLE_DISCONNECT   BIT(14)
	Bit for message disable disconnect.
#define	TCPC_REG_DEV_CAP_2_GENERIC_TIMER   BIT(13)
	Bit for generic timer support.
#define	TCPC_REG_DEV_CAP_2_LONG_MSG   BIT(12)
	Bit for long message support If set, the TCPC supports up to 264 bytes content of the SOP*.
#define	TCPC_REG_DEV_CAP_2_SMBUS_PEC   BIT(11)
	Bit for SMBus PEC support.
#define	TCPC_REG_DEV_CAP_2_SRC_FRS   BIT(10)
	Bit for source fast-role swap support.
#define	TCPC_REG_DEV_CAP_2_SNK_FRS   BIT(9)
	Bit for sink fast-role swap support.
#define	TCPC_REG_DEV_CAP_2_WATCHDOG_TIMER   BIT(8)
	Bit for watchdog timer support.
#define	TCPC_REG_DEV_CAP_2_SNK_DISC_DET   BIT(7)
	Bit for sink disconnect detection.
#define	TCPC_REG_DEV_CAP_2_STOP_DISCHARGE_THRESH   BIT(6)
	Bit for stop discharge threshold.
#define	TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK   GENMASK(5, 4)
	Mask for resolution of voltage alarm.
#define	TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM(reg)
	Macro to extract the voltage alarm resolution from the register value.
#define	TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_25MV   0
	Value for 25mV resolution of voltage alarm, all 10 bits of voltage alarm registers are used.
#define	TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_50MV   1
	Value for 50mV resolution of voltage alarm, only 9 bits of voltage alarm registers are used.
#define	TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_100MV   2
	Value for 100mV resolution of voltage alarm, only 8 bits of voltage alarm registers are used.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK   GENMASK(3, 1)
	Mask for vconn power supported.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED(reg)
	Macro to extract the vconn power supported from the register value.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_0W   0
	Value for vconn power supported of 1.0W.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_5W   1
	Value for vconn power supported of 1.5W.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_2_0W   2
	Value for vconn power supported of 2.0W.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_3_0W   3
	Value for vconn power supported of 3.0W.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_4_0W   4
	Value for vconn power supported of 4.0W.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_5_0W   5
	Value for vconn power supported of 5.0W.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_6_0W   6
	Value for vconn power supported of 6.0W.
#define	TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_EXTERNAL   7
	Value for external vconn power supported.
#define	TCPC_REG_DEV_CAP_2_VCONN_OVC_FAULT   BIT(0)
	Bit for vconn overcurrent fault capable - if set, TCPC can detect the vconn over current.
#define	TCPC_REG_STD_INPUT_CAP   0x28
	Register address - standard input capabilities.
#define	TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK   GENMASK(4, 3)
	Mask for source fast role swap.
#define	TCPC_REG_STD_INPUT_CAP_SRC_FRS(reg)
	Macro to extract the source fast role swap from register value.
#define	TCPC_REG_STD_INTPU_CAP_SRC_FRS_NONE   0
	Value for no source fast role swap pin present in TCPC.
#define	TCPC_REG_STD_INTPU_CAP_SRC_FRS_INPUT   1
	Value for source fast role swap input only pin present in TCPC.
#define	TCPC_REG_STD_INTPU_CAP_SRC_FRS_BOTH   2
	Value for source fast role swap both input and output pin present in TCPC.
#define	TCPC_REG_STD_INPUT_CAP_EXT_OVP   BIT(2)
	Bit for vbus external over voltage fault.
#define	TCPC_REG_STD_INPUT_CAP_EXT_OCP   BIT(1)
	Bit for vbus external over current fault.
#define	TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS   BIT(0)
	Bit for force off vbus present.
#define	TCPC_REG_STD_OUTPUT_CAP   0x29
	Register address - standard output capabilities.
#define	TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET   BIT(7)
	Bit for vbus sink disconnect detect indicator.
#define	TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY   BIT(6)
	Bit for debug accessory indicator.
#define	TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON   BIT(5)
	Bit for vbus present monitor.
#define	TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY   BIT(4)
	Bit for audio adapter accessory indicator.
#define	TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE   BIT(3)
	Bit for active cable indicator.
#define	TCPC_REG_STD_OUTPUT_CAP_MUX_CFG_CTRL   BIT(2)
	Bit for mux configuration control.
#define	TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT   BIT(1)
	Bit for connection present.
#define	TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION   BIT(0)
	Bit for connector orientation.
#define	TCPC_REG_CONFIG_EXT_1   0x2A
	Register address - configure extended 1.
#define	TCPC_REG_CONFIG_EXT_1_FRS_SNK_DIR   BIT(1)
	Bit for fr swap bidirectional pin.
#define	TCPC_REG_CONFIG_EXT_1_STD_IN_SRC_FRS   BIT(0)
	Bit for standard input source FR swap.
#define	TCPC_REG_GENERIC_TIMER   0x2c
	Register address - generic timer Available only if generic timer bit is set in device capabilities 2 register.
#define	TCPC_REG_MSG_HDR_INFO   0x2e
	Register address - message header info.
#define	TCPC_REG_MSG_HDR_INFO_CABLE_PLUG   BIT(4)
	Bit for cable plug.
#define	TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK   BIT(3)
	Mask for data role.
#define	TCPC_REG_MSG_HDR_INFO_DATA_ROLE(reg)
	Macro to extract the data role from register value.
#define	TCPC_REG_MSG_HDR_INFO_DATA_ROLE_UFP   0
	Value for data role set as UFP.
#define	TCPC_REG_MSG_HDR_INFO_DATA_ROLE_DFP   1
	Value for data role set as DFP.
#define	TCPC_REG_MSG_HDR_INFO_PD_REV_MASK   GENMASK(2, 1)
	Mask for Power Delivery Specification Revision.
#define	TCPC_REG_MSG_HDR_INFO_PD_REV(reg)
	Macro to extract the Power Delivery Specification Revision from register value.
#define	TCPC_REG_MSG_HDR_INFO_PD_REV_1_0   0
	Value for Power Delivery Specification Revision 1.0.
#define	TCPC_REG_MSG_HDR_INFO_PD_REV_2_0   1
	Value for Power Delivery Specification Revision 2.0.
#define	TCPC_REG_MSG_HDR_INFO_PD_REV_3_0   2
	Value for Power Delivery Specification Revision 3.0.
#define	TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK   BIT(0)
	Mask for power role.
#define	TCPC_REG_MSG_HDR_INFO_POWER_ROLE(reg)
	Macro to extract the power role from register value.
#define	TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SNK   0
	Value for power role set as sink.
#define	TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SRC   1
	Value for power role set as source.
#define	TCPC_REG_MSG_HDR_INFO_SET(pd_rev_type, drole, prole)
	Macro to set the register value with pd revision, data and power role from parameter and as non-cable plug.
#define	TCPC_REG_MSG_HDR_INFO_ROLES_MASK   (TCPC_REG_MSG_HDR_INFO_SET(3, 1, 1))
	Mask for PD revision and power and data role.
#define	TCPC_REG_RX_DETECT   0x2f
	Register address - receive detect.
#define	TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT   BIT(7)
	Bit for message disable disconnect.
#define	TCPC_REG_RX_DETECT_CABLE_RST   BIT(6)
	Bit for enable cable reset.
#define	TCPC_REG_RX_DETECT_HRST   BIT(5)
	Bit for enable hard reset.
#define	TCPC_REG_RX_DETECT_SOPPP_DBG   BIT(4)
	Bit for enable SOP_DBG'' message.
#define	TCPC_REG_RX_DETECT_SOPP_DBG   BIT(3)
	Bit for enable SOP_DBG' message.
#define	TCPC_REG_RX_DETECT_SOPPP   BIT(2)
	Bit for enable SOP'' message.
#define	TCPC_REG_RX_DETECT_SOPP   BIT(1)
	Bit for enable SOP' message.
#define	TCPC_REG_RX_DETECT_SOP   BIT(0)
	Bit for enable SOP message.
#define	TCPC_REG_RX_DETECT_SOP_HRST_MASK   (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST)
	Mask for detecting the SOP messages and hard reset signals.
#define	TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK
	Mask for detecting the SOP, SOP' and SOP'' messages and hard reset signals.
#define	TCPC_REG_RX_BUFFER   0x30
	Register address - receive buffer (readable byte count, rx buf frame type, rx buf byte x) In TCPC Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers: READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x.
#define	TCPC_REG_TRANSMIT   0x50
	Register address - transmit.
#define	TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type)
	Macro to set the transmit register with message type and retries count.
#define	TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type)
	Macro to set the transmit register with message type and without retries.
#define	TCPC_REG_TRANSMIT_TYPE_SOP   0
	Value for transmit SOP type message.
#define	TCPC_REG_TRANSMIT_TYPE_SOPP   1
	Value for transmit SOP' type message.
#define	TCPC_REG_TRANSMIT_TYPE_SOPPP   2
	Value for transmit SOP'' type message.
#define	TCPC_REG_TRANSMIT_TYPE_SOP_DBG_P   3
	Value for transmit SOP_DBG' type message.
#define	TCPC_REG_TRANSMIT_TYPE_SOP_DBG_PP   4
	Value for transmit SOP_DBG'' type message.
#define	TCPC_REG_TRANSMIT_TYPE_HRST   5
	Value for transmit hard reset signal.
#define	TCPC_REG_TRANSMIT_TYPE_CABLE_RST   6
	Value for transmit cable reset signal.
#define	TCPC_REG_TRANSMIT_TYPE_BIST   7
	Value for transmit BIST carrier mode 2.
#define	TCPC_REG_TX_BUFFER   0x51
	Register address - transmit buffer In TCPC Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the portion of the SOP* USB PD message payload (including the header and/or the data bytes) most recently written by the TCPM in TX_BUF_BYTE_x.
#define	TCPC_REG_VBUS_VOLTAGE   0x70
	Register address - vbus voltage.
#define	TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK   GENMASK(9, 0)
	Mask for vbus voltage measurement.
#define	TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(reg)
	Macro to extract the vbus measurement from the register value.
#define	TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK   GENMASK(11, 10)
	Mask for scale factor.
#define	TCPC_REG_VBUS_VOLTAGE_SCALE(reg)
	Macro to extract the vbus voltage scale from the register value.
#define	TCPC_REG_VBUS_VOLTAGE_LSB   25
	Resolution of vbus voltage measurement.
#define	TCPC_REG_VBUS_VOLTAGE_VBUS(x)
	Macro to convert the register value into real voltage measurement taking scale factor into account.
#define	TCPC_REG_VBUS_SINK_DISCONNECT_THRESH   0x72
	Register address - vbus sink disconnect threshold.
#define	TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_LSB   25
	Resolution of the value stored in register.
#define	TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_MASK   GENMASK(11, 0)
	Mask for the valid bits of voltage trip point.
#define	TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT   0x008C /* 3.5 V */
	Default value for vbus sink disconnect threshold.
#define	TCPC_REG_VBUS_STOP_DISCHARGE_THRESH   0x74
	Register address - vbus sink disconnect threshold.
#define	TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_LSB   25
	Resolution of the value stored in register.
#define	TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_MASK   GENMASK(11, 0)
	Mask for the valid bits of voltage trip point.
#define	TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_DEFAULT   0x0020 /* 0.8 V */
	Default value for vbus stop discharge threshold.
#define	TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG   0x76
	Register address - vbus voltage alarm - high.
#define	TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_LSB   25
	Resolution of the value stored in register.
#define	TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_MASK   GENMASK(11, 0)
	Mask for the valid bits of voltage trip point.
#define	TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG   0x78
	Register address - vbus voltage alarm - low.
#define	TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_LSB   25
	Resolution of the value stored in register.
#define	TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_MASK   GENMASK(11, 0)
	Mask for the valid bits of voltage trip point.
#define	TCPC_REG_VBUS_NONDEFAULT_TARGET   0x7a
	Register address - vbus nondefault target Available only if vbus nondefault target is asserted in device capabilities 1 register.
#define	TCPC_REG_VBUS_NONDEFAULT_TARGET_LSB   20
	Resolution of the value stored in register.
#define	TCPC_REG_DEV_CAP_3   0x7c
	Register address - device capabilities 3.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK   GENMASK(2, 0)
	Mask for vbus voltage support.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX(reg)
	Macro to extract the vbus voltage support from register value.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_5V   0
	Value for nominal voltage supported of 5V.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_9V   1
	Value for nominal voltage supported of 9V.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_15V   2
	Value for nominal voltage supported of 15V.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_20V   3
	Value for nominal voltage supported of 20V.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_28V   4
	Value for nominal voltage supported of 28V.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_36V   5
	Value for nominal voltage supported of 36V.
#define	TCPC_REG_DEV_CAP_3_VBUS_MAX_48V   6
	Value for nominal voltage supported of 48V.

Detailed Description

Registers and fields definitions for TypeC Port Controller Interface.

This file contains register addresses, fields and masks used to retrieve specific data from registry values. They may be used by all TCPC drivers compliant to the TCPCI specification. Registers and fields are compliant to the Type-C Port Controller Interface Specification Revision 2.0, Version 1.3.

Macro Definition Documentation

TCPC_REG_ALERT

#define TCPC_REG_ALERT   0x10

Register address - alert.

TCPC_REG_ALERT_ALERT_EXT

#define TCPC_REG_ALERT_ALERT_EXT   BIT(14)

Bit for extended alert.

TCPC_REG_ALERT_CC_STATUS

#define TCPC_REG_ALERT_CC_STATUS   BIT(0)

Bit for CC lines status alert.

TCPC_REG_ALERT_EXT

#define TCPC_REG_ALERT_EXT   0x21

Register address - alert extended.

TCPC_REG_ALERT_EXT_MASK

#define TCPC_REG_ALERT_EXT_MASK   0x17

Register address - extended alert mask The bits for specific masks are on the same positions as for the.

See also

TCPC_REG_ALERT_EXT register.

TCPC_REG_ALERT_EXT_SNK_FRS

#define TCPC_REG_ALERT_EXT_SNK_FRS   BIT(0)

Bit for sink fast role swap.

If set, the fast role swap signal was received.

TCPC_REG_ALERT_EXT_SRC_FRS

#define TCPC_REG_ALERT_EXT_SRC_FRS   BIT(1)

Bit for source fast role swap.

Set when FRS signal sent due to standard input being low.

TCPC_REG_ALERT_EXT_STATUS

#define TCPC_REG_ALERT_EXT_STATUS   BIT(13)

Bit for extended status alert.

TCPC_REG_ALERT_EXT_TIMER_EXPIRED

#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED   BIT(2)

Bit for timer expired.

TCPC_REG_ALERT_FAULT

#define TCPC_REG_ALERT_FAULT   BIT(9)

Bit for fault alert.

TCPC_REG_ALERT_MASK

#define TCPC_REG_ALERT_MASK   0x12

Register address - alert mask The bits for specific masks are on the same positions as for the.

See also

TCPC_REG_ALERT register.

TCPC_REG_ALERT_MASK_ALL

#define TCPC_REG_ALERT_MASK_ALL   0xffff

Value mask for all alert bits.

TCPC_REG_ALERT_NONE

#define TCPC_REG_ALERT_NONE   0x0000

Value for clear alert.

TCPC_REG_ALERT_POWER_STATUS

#define TCPC_REG_ALERT_POWER_STATUS   BIT(1)

Bit for power status alert.

TCPC_REG_ALERT_RX_BEGINNING

#define TCPC_REG_ALERT_RX_BEGINNING   BIT(12)

Bit for beginning of data receive.

TCPC_REG_ALERT_RX_BUF_OVF

#define TCPC_REG_ALERT_RX_BUF_OVF   BIT(10)

Bit for receive buffer overflow alert.

TCPC_REG_ALERT_RX_HARD_RST

#define TCPC_REG_ALERT_RX_HARD_RST   BIT(3)

Bit for received hard reset alert.

TCPC_REG_ALERT_RX_STATUS

#define TCPC_REG_ALERT_RX_STATUS   BIT(2)

Bit for data received alert.

TCPC_REG_ALERT_TX_COMPLETE

#define TCPC_REG_ALERT_TX_COMPLETE    (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_TX_FAILED)

Bits for any of transmission status alert.

TCPC_REG_ALERT_TX_DISCARDED

#define TCPC_REG_ALERT_TX_DISCARDED   BIT(5)

Bit for transmission discard alert.

TCPC_REG_ALERT_TX_FAILED

#define TCPC_REG_ALERT_TX_FAILED   BIT(4)

Bit for transmission fail alert.

TCPC_REG_ALERT_TX_SUCCESS

#define TCPC_REG_ALERT_TX_SUCCESS   BIT(6)

Bit for transmission success.

TCPC_REG_ALERT_V_ALARM_HI

#define TCPC_REG_ALERT_V_ALARM_HI   BIT(7)

Bit for high vbus alarm.

TCPC_REG_ALERT_V_ALARM_LO

#define TCPC_REG_ALERT_V_ALARM_LO   BIT(8)

Bit for low vbus alarm.

TCPC_REG_ALERT_VBUS_DISCNCT

#define TCPC_REG_ALERT_VBUS_DISCNCT   BIT(11)

Bit for vbus disconnection alert.

TCPC_REG_ALERT_VENDOR_DEF

#define TCPC_REG_ALERT_VENDOR_DEF   BIT(15)

Bit for vendor defined alert.

TCPC_REG_BCD_DEV

#define TCPC_REG_BCD_DEV   0x4

Register address - version of TCPC.

TCPC_REG_CC_STATUS

#define TCPC_REG_CC_STATUS   0x1d

Register address - CC lines status.

TCPC_REG_CC_STATUS_CC1_STATE

#define TCPC_REG_CC_STATUS_CC1_STATE

(

reg

)

Value:

((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)

Macto to extract the status value of CC1 line.

Look at the information about the CC2 macro.

TCPC_REG_CC_STATUS_CC1_STATE_MASK

#define TCPC_REG_CC_STATUS_CC1_STATE_MASK   GENMASK(1, 0)

Mask for CC1 line state.

TCPC_REG_CC_STATUS_CC2_STATE

#define TCPC_REG_CC_STATUS_CC2_STATE

(

reg

)

Value:

(((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)

Macro to extract the status value of CC2 line.

Interpretation of this value depends on the value of CC2 configuration in Role Control register and on the connect result in this register. For value interpretation look at the CC_STATUS Register Definition in the TCPCI specification.

TCPC_REG_CC_STATUS_CC2_STATE_MASK

#define TCPC_REG_CC_STATUS_CC2_STATE_MASK   GENMASK(3, 2)

Mask for CC2 line state.

TCPC_REG_CC_STATUS_CONNECT_RESULT

#define TCPC_REG_CC_STATUS_CONNECT_RESULT   BIT(4)

Bit for connection result, set if presenting Rd, unset if presenting Rp.

TCPC_REG_CC_STATUS_LOOK4CONNECTION

#define TCPC_REG_CC_STATUS_LOOK4CONNECTION   BIT(5)

Bit for active looking for a connection by TCPC, both DRP and sink/source only.

TCPC_REG_COMMAND

#define TCPC_REG_COMMAND   0x23

Register address - command.

TCPC_REG_COMMAND_DISABLE_VBUS_DETECT

#define TCPC_REG_COMMAND_DISABLE_VBUS_DETECT   0x22

Value for disable vbus detect command - disable vbus present and vSafe0V detection.

TCPC_REG_COMMAND_ENABLE_VBUS_DETECT

#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT   0x33

Value for enable vbus detect command - enable vbus present and vSafe0V detection.

TCPC_REG_COMMAND_I2CIDLE

#define TCPC_REG_COMMAND_I2CIDLE   0xFF

Value for i2c idle.

TCPC_REG_COMMAND_LOOK4CONNECTION

#define TCPC_REG_COMMAND_LOOK4CONNECTION   0x99

Value for look for connection - start DRP toggling if DRP role is set.

TCPC_REG_COMMAND_RESET_RECEIVE_BUF

#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF   0xEE

Value for reset receive buffer If buffer pointer is at 132 or less, it is reset to 1, otherwise it is reset to 133.

TCPC_REG_COMMAND_RESET_TRANSMIT_BUF

#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF   0xDD

Value for reset transmit buffer - TCPC resets the pointer of transmit buffer to offset 1.

TCPC_REG_COMMAND_RX_ONE_MORE

#define TCPC_REG_COMMAND_RX_ONE_MORE   0xAA

Value for rx one more Configure receiver to automatically clear the receive_detect register after sending next GoodCRC.

TCPC_REG_COMMAND_SEND_FRS_SIGNAL

#define TCPC_REG_COMMAND_SEND_FRS_SIGNAL   0xCC

Value for send fast role swap signal Send FRS if TCPC is source with FRS enabled in power control register.

TCPC_REG_COMMAND_SNK_CTRL_HIGH

#define TCPC_REG_COMMAND_SNK_CTRL_HIGH   0x55

Value for sink vbus - enable sinking power over vbus and vbus present detection.

TCPC_REG_COMMAND_SNK_CTRL_LOW

#define TCPC_REG_COMMAND_SNK_CTRL_LOW   0x44

Value for disable sink vbus - disable sinking power over vbus.

TCPC_REG_COMMAND_SRC_CTRL_DEF

#define TCPC_REG_COMMAND_SRC_CTRL_DEF   0x77

Value for source vbus default voltage - enable sourcing vSafe5V over vbus.

TCPC_REG_COMMAND_SRC_CTRL_HV

#define TCPC_REG_COMMAND_SRC_CTRL_HV   0x88

Value for source vbus high voltage - enable sourcing high voltage over vbus.

TCPC_REG_COMMAND_SRC_CTRL_LOW

#define TCPC_REG_COMMAND_SRC_CTRL_LOW   0x66

Value for disable source vbus - disable sourcing power over vbus.

TCPC_REG_COMMAND_WAKE_I2C

#define TCPC_REG_COMMAND_WAKE_I2C   0x11

Value for wake i2c command.

TCPC_REG_CONFIG_EXT_1

#define TCPC_REG_CONFIG_EXT_1   0x2A

Register address - configure extended 1.

TCPC_REG_CONFIG_EXT_1_FRS_SNK_DIR

#define TCPC_REG_CONFIG_EXT_1_FRS_SNK_DIR   BIT(1)

Bit for fr swap bidirectional pin.

If set, the bidirectional FR swap pin is configured as standard output signal. If unset, it's configured as standard input signal.

TCPC_REG_CONFIG_EXT_1_STD_IN_SRC_FRS

#define TCPC_REG_CONFIG_EXT_1_STD_IN_SRC_FRS   BIT(0)

Bit for standard input source FR swap.

If set, blocks the source fast role swap input signal from triggering the sending of fast role swap signal. If unset, allow the input signal to trigger sending the fast role swap signal.

TCPC_REG_CONFIG_STD_OUTPUT

#define TCPC_REG_CONFIG_STD_OUTPUT   0x18

Register address - configure standard output.

TCPC_REG_CONFIG_STD_OUTPUT_ACTIVE_CABLE

#define TCPC_REG_CONFIG_STD_OUTPUT_ACTIVE_CABLE   BIT(4)

Bit for active cable.

TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N

#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N   BIT(5)

Bit for audio accessory connected#.

TCPC_REG_CONFIG_STD_OUTPUT_CONN_PRESENT

#define TCPC_REG_CONFIG_STD_OUTPUT_CONN_PRESENT   BIT(1)

Bit for connection present.

TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED

#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED   BIT(0)

Bit for connector orientation.

TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N

#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N   BIT(6)

Bit for debug accessory connected#.

TCPC_REG_CONFIG_STD_OUTPUT_HIGH_Z

#define TCPC_REG_CONFIG_STD_OUTPUT_HIGH_Z   BIT(7)

Bit for high impedance outputs.

TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP

#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP   (2 << 2)

Value for mux - DP alternate mode with 4 lanes.

TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK

#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK   (3 << 2)

Value mask for mux control.

TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE

#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE   (0 << 2)

Value for mux - no connection.

TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB

#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB   (1 << 2)

Value for mux - USB3.1 connected.

TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB_DP

#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB_DP   (3 << 2)

Value for mux - USB3.1 + DP 0&1 lines.

TCPC_REG_DEV_CAP_1

#define TCPC_REG_DEV_CAP_1   0x24

Register address - device capabilities 1.

TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED

#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED   BIT(4)

Bit for debug SOP' and SOP'' support - if set, all SOP* messages are supported.

TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE

#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE   BIT(12)

Bit for bleed discharge - if set, bleed discharge is implemented in TCPC.

TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE

#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE   BIT(11)

Bit for force discharge - if set, force discharge is implemented in TCPC.

TCPC_REG_DEV_CAP_1_POWER_ROLE

#define TCPC_REG_DEV_CAP_1_POWER_ROLE

(

reg

)

Value:

        (((reg) & TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK) >> 5)

TCPC_REG_DEV_CAP_1_POWER_ROLE_DRP

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_DRP   4

Value for support dual-role port only.

TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK   GENMASK(7, 5)

Mask for power roles supported.

TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK   2

Value for support sink role only.

TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK_ACC

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK_ACC   3

Value for support sink role with accessory.

TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC   1

Value for support source role only.

TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_OR_SNK

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_OR_SNK   0

Value for support both source and sink only (no DRP)

TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP   6

Value for support source, sink and dual-role port.

TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP_ADPT_CBL

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP_ADPT_CBL   5

Value for support source, sink, dual-role port, adapter and cable.

TCPC_REG_DEV_CAP_1_SINK_VBUS

#define TCPC_REG_DEV_CAP_1_SINK_VBUS   BIT(2)

Bit for sink vbus - if set, TCPC is capable of controling the sink path to the system load.

TCPC_REG_DEV_CAP_1_SOURCE_HV_VBUS

#define TCPC_REG_DEV_CAP_1_SOURCE_HV_VBUS   BIT(1)

Bit for source high voltage vbus.

If set, TCPC can control the source high voltage path to vbus

TCPC_REG_DEV_CAP_1_SOURCE_VBUS

#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS   BIT(0)

Bit for source vbus - if set, TCPC is capable of controlling the source path to vbus.

TCPC_REG_DEV_CAP_1_SOURCE_VCONN

#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN   BIT(3)

Bit for source vconn - if set, TCPC is capable of switching the vconn source.

TCPC_REG_DEV_CAP_1_SRC_RESISTOR

#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR

(

reg

)

Value:

        (((reg) & TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK) >> 8)

Macro to extract the supported source resistors from register value The value can be cast to enum tc_rp_value and value can be treated as highest amperage supported since the TCPC has also to support lower values than specified.

TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK

#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK   GENMASK(9, 8)

Mask for source resistor supported.

TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF

#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF   1

Value for Rp 1.5A and default - support for 1.5A and for default amperage.

TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF

#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF   2

Value for Rp 3.0A, 1.5A and default - support for 3.0A, 1.5A and default amperage.

TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF

#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF   0

Value for Rp default only - only default amperage is supported.

TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE

#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE   BIT(10)

Bit for vbus measurement and alarm capable If set, TCPC supports vbus voltage measurement and vbus voltage alarms.

TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET

#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET   BIT(15)

Bit for vbus high voltage target - if set, VBUS_HV_TARGET register is implemented.

TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING

#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING   BIT(14)

Bit for vbus over current reporting - if set, vbus over current is reported by TCPC.

TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING

#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING   BIT(13)

Bit for vbus over voltage reporting - if set, vbus over voltage is reported by TCPC.

TCPC_REG_DEV_CAP_2

#define TCPC_REG_DEV_CAP_2   0x26

Register address - device capabilities 2.

TCPC_REG_DEV_CAP_2_CAP_3_SUPPORTED

#define TCPC_REG_DEV_CAP_2_CAP_3_SUPPORTED   BIT(15)

Bit for device capabilities 3 support.

TCPC_REG_DEV_CAP_2_GENERIC_TIMER

#define TCPC_REG_DEV_CAP_2_GENERIC_TIMER   BIT(13)

Bit for generic timer support.

TCPC_REG_DEV_CAP_2_LONG_MSG

#define TCPC_REG_DEV_CAP_2_LONG_MSG   BIT(12)

Bit for long message support If set, the TCPC supports up to 264 bytes content of the SOP*.

One I2C transaction can write up to 132 bytes. If unset, the TCPC support only 30 bytes content of the SOP* message.

TCPC_REG_DEV_CAP_2_MSG_DISABLE_DISCONNECT

#define TCPC_REG_DEV_CAP_2_MSG_DISABLE_DISCONNECT   BIT(14)

Bit for message disable disconnect.

TCPC_REG_DEV_CAP_2_SMBUS_PEC

#define TCPC_REG_DEV_CAP_2_SMBUS_PEC   BIT(11)

Bit for SMBus PEC support.

If set, SMBus PEC can be enabled in the TCPC control register.

TCPC_REG_DEV_CAP_2_SNK_DISC_DET

#define TCPC_REG_DEV_CAP_2_SNK_DISC_DET   BIT(7)

Bit for sink disconnect detection.

If set, the sink disconnect threshold can be set. Otherwise, the vbus present value from status register will be used to indicate the sink disconnection.

TCPC_REG_DEV_CAP_2_SNK_FRS

#define TCPC_REG_DEV_CAP_2_SNK_FRS   BIT(9)

Bit for sink fast-role swap support.

If set, TCPC is capable of sending FRS as sink.

TCPC_REG_DEV_CAP_2_SRC_FRS

#define TCPC_REG_DEV_CAP_2_SRC_FRS   BIT(10)

Bit for source fast-role swap support.

If set, TCPC is capable of sending FRS as source.

TCPC_REG_DEV_CAP_2_STOP_DISCHARGE_THRESH

#define TCPC_REG_DEV_CAP_2_STOP_DISCHARGE_THRESH   BIT(6)

Bit for stop discharge threshold.

If set, the TCPM can set the voltage threshold at which the forced vbus discharge will be disabled, into the vbus stop discharge threshold register.

TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM

#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM

(

reg

)

Value:

        (((reg) & TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK) >> 4)

Macro to extract the voltage alarm resolution from the register value.

TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_100MV

#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_100MV   2

Value for 100mV resolution of voltage alarm, only 8 bits of voltage alarm registers are used.

TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_25MV

#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_25MV   0

Value for 25mV resolution of voltage alarm, all 10 bits of voltage alarm registers are used.

TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_50MV

#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_50MV   1

Value for 50mV resolution of voltage alarm, only 9 bits of voltage alarm registers are used.

TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK

#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK   GENMASK(5, 4)

Mask for resolution of voltage alarm.

TCPC_REG_DEV_CAP_2_VCONN_OVC_FAULT

#define TCPC_REG_DEV_CAP_2_VCONN_OVC_FAULT   BIT(0)

Bit for vconn overcurrent fault capable - if set, TCPC can detect the vconn over current.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED

(

reg

)

Value:

        (((reg) & TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK) >> 1)

Macro to extract the vconn power supported from the register value.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_0W

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_0W   0

Value for vconn power supported of 1.0W.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_5W

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_5W   1

Value for vconn power supported of 1.5W.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_2_0W

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_2_0W   2

Value for vconn power supported of 2.0W.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_3_0W

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_3_0W   3

Value for vconn power supported of 3.0W.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_4_0W

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_4_0W   4

Value for vconn power supported of 4.0W.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_5_0W

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_5_0W   5

Value for vconn power supported of 5.0W.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_6_0W

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_6_0W   6

Value for vconn power supported of 6.0W.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_EXTERNAL

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_EXTERNAL   7

Value for external vconn power supported.

TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK   GENMASK(3, 1)

Mask for vconn power supported.

TCPC_REG_DEV_CAP_2_WATCHDOG_TIMER

#define TCPC_REG_DEV_CAP_2_WATCHDOG_TIMER   BIT(8)

Bit for watchdog timer support.

If set, watchdog can be enabled in the TCPC control register.

TCPC_REG_DEV_CAP_3

#define TCPC_REG_DEV_CAP_3   0x7c

Register address - device capabilities 3.

TCPC_REG_DEV_CAP_3_VBUS_MAX

#define TCPC_REG_DEV_CAP_3_VBUS_MAX

(

reg

)

Value:

((reg) & TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK)

Macro to extract the vbus voltage support from register value.

TCPC_REG_DEV_CAP_3_VBUS_MAX_15V

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_15V   2

Value for nominal voltage supported of 15V.

TCPC_REG_DEV_CAP_3_VBUS_MAX_20V

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_20V   3

Value for nominal voltage supported of 20V.

TCPC_REG_DEV_CAP_3_VBUS_MAX_28V

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_28V   4

Value for nominal voltage supported of 28V.

TCPC_REG_DEV_CAP_3_VBUS_MAX_36V

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_36V   5

Value for nominal voltage supported of 36V.

TCPC_REG_DEV_CAP_3_VBUS_MAX_48V

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_48V   6

Value for nominal voltage supported of 48V.

TCPC_REG_DEV_CAP_3_VBUS_MAX_5V

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_5V   0

Value for nominal voltage supported of 5V.

TCPC_REG_DEV_CAP_3_VBUS_MAX_9V

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_9V   1

Value for nominal voltage supported of 9V.

TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK

#define TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK   GENMASK(2, 0)

Mask for vbus voltage support.

TCPC_REG_EXT_STATUS

#define TCPC_REG_EXT_STATUS   0x20

Register address - extended status.

TCPC_REG_EXT_STATUS_MASK

#define TCPC_REG_EXT_STATUS_MASK   0x16

Register address - extended status mask The bits for specific masks are on the same positions as for the.

See also

TCPC_REG_EXT_STATUS register.

TCPC_REG_EXT_STATUS_SAFE0V

#define TCPC_REG_EXT_STATUS_SAFE0V   BIT(0)

Bit for vbus at vSafe0V.

Set when the TCPC detects that VBUS is below 0.8V.

TCPC_REG_FAULT_CTRL

#define TCPC_REG_FAULT_CTRL   0x1b

Register address - fault control.

TCPC_REG_FAULT_CTRL_VBUS_DISCHARGE_FAULT

#define TCPC_REG_FAULT_CTRL_VBUS_DISCHARGE_FAULT   BIT(3)

Bit for disabling the vbus discharge fault detection timer.

TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF

#define TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF   BIT(4)

Bit for block the standard input signal force off vbus control.

TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS

#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS   BIT(2)

Bit for disabling the vbus over current detection.

TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS

#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS   BIT(1)

Bit for disabling the vbus over voltage detection.

TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS

#define TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS   BIT(0)

Bit for disabling the vconn over current detection.

TCPC_REG_FAULT_STATUS

#define TCPC_REG_FAULT_STATUS   0x1f

Register address - fault status.

TCPC_REG_FAULT_STATUS_ALL_REGS_RESET

#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET   BIT(7)

Bit for all registers reset to default.

TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL

#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL   BIT(5)

Bit for auto discharge failed.

TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL

#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL   BIT(4)

Bit for force discharge failed.

TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS

#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS   BIT(6)

Bit for force vbus off due to external fault.

TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR

#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR   BIT(0)

Bit for I2C interface error.

TCPC_REG_FAULT_STATUS_MASK

#define TCPC_REG_FAULT_STATUS_MASK   0x15

Register address - fault status mask The bits for specific masks are on the same positions as for the.

See also

TCPC_REG_FAULT_STATUS register.

TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT

#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT   BIT(3)

Bit for internal or external vbus over current.

TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE

#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE   BIT(2)

Bit for internal or external vbus over voltage.

TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT

#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT   BIT(1)

Bit for vconn over current.

TCPC_REG_GENERIC_TIMER

#define TCPC_REG_GENERIC_TIMER   0x2c

Register address - generic timer Available only if generic timer bit is set in device capabilities 2 register.

This register is 16-bit wide and has a resolution of 0.1ms.

TCPC_REG_MSG_HDR_INFO

#define TCPC_REG_MSG_HDR_INFO   0x2e

Register address - message header info.

TCPC_REG_MSG_HDR_INFO_CABLE_PLUG

#define TCPC_REG_MSG_HDR_INFO_CABLE_PLUG   BIT(4)

Bit for cable plug.

If set, the message originated from a cable plug.

TCPC_REG_MSG_HDR_INFO_DATA_ROLE

#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE

(

reg

)

Value:

(((reg) & TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK) >> 3)

Macro to extract the data role from register value.

TCPC_REG_MSG_HDR_INFO_DATA_ROLE_DFP

#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_DFP   1

Value for data role set as DFP.

TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK

#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK   BIT(3)

Mask for data role.

TCPC_REG_MSG_HDR_INFO_DATA_ROLE_UFP

#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_UFP   0

Value for data role set as UFP.

TCPC_REG_MSG_HDR_INFO_PD_REV

#define TCPC_REG_MSG_HDR_INFO_PD_REV

(

reg

)

Value:

(((reg) & TCPC_REG_MSG_HDR_INFO_PD_REV_MASK) >> 1)

Macro to extract the Power Delivery Specification Revision from register value.

TCPC_REG_MSG_HDR_INFO_PD_REV_1_0

#define TCPC_REG_MSG_HDR_INFO_PD_REV_1_0   0

Value for Power Delivery Specification Revision 1.0.

TCPC_REG_MSG_HDR_INFO_PD_REV_2_0

#define TCPC_REG_MSG_HDR_INFO_PD_REV_2_0   1

Value for Power Delivery Specification Revision 2.0.

TCPC_REG_MSG_HDR_INFO_PD_REV_3_0

#define TCPC_REG_MSG_HDR_INFO_PD_REV_3_0   2

Value for Power Delivery Specification Revision 3.0.

TCPC_REG_MSG_HDR_INFO_PD_REV_MASK

#define TCPC_REG_MSG_HDR_INFO_PD_REV_MASK   GENMASK(2, 1)

Mask for Power Delivery Specification Revision.

TCPC_REG_MSG_HDR_INFO_POWER_ROLE

#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE

(

reg

)

Value:

((reg) & TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK)

Macro to extract the power role from register value.

TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK

#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK   BIT(0)

Mask for power role.

TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SNK

#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SNK   0

Value for power role set as sink.

TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SRC

#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SRC   1

Value for power role set as source.

TCPC_REG_MSG_HDR_INFO_ROLES_MASK

#define TCPC_REG_MSG_HDR_INFO_ROLES_MASK   (TCPC_REG_MSG_HDR_INFO_SET(3, 1, 1))

Mask for PD revision and power and data role.

TCPC_REG_MSG_HDR_INFO_SET

#define TCPC_REG_MSG_HDR_INFO_SET	(		pd_rev_type,
			drole,
			prole )

Value:

        ((drole) << 3 | (pd_rev_type << 1) | (prole))

Macro to set the register value with pd revision, data and power role from parameter and as non-cable plug.

TCPC_REG_PD_INT_REV

#define TCPC_REG_PD_INT_REV   0xa

Register address - interface revision and version.

TCPC_REG_PD_INT_REV_REV_MAJOR

#define TCPC_REG_PD_INT_REV_REV_MAJOR

(

reg

)

Value:

(((reg) & TCPC_REG_PD_REV_VER_REV_MAJOR_MASK) >> 12)

Macro to extract the major part of USB Port Controller Interface revision supported.

TCPC_REG_PD_INT_REV_REV_MAJOR_MASK

#define TCPC_REG_PD_INT_REV_REV_MAJOR_MASK   GENMASK(15, 12)

Mask for major part of USB Port Controller Interface revision supported.

TCPC_REG_PD_INT_REV_REV_MINOR

#define TCPC_REG_PD_INT_REV_REV_MINOR

(

reg

)

Value:

(((reg) & TCPC_REG_PD_REV_VER_REV_MINOR_MASK) >> 8)

Macro to extract the minor part of USB Port Controller Interface revision supported.

TCPC_REG_PD_INT_REV_REV_MINOR_MASK

#define TCPC_REG_PD_INT_REV_REV_MINOR_MASK   GENMASK(11, 8)

Mask for minor part of USB Port Controller Interface revision supported.

TCPC_REG_PD_INT_REV_VER_MAJOR

#define TCPC_REG_PD_INT_REV_VER_MAJOR

(

reg

)

Value:

(((reg) & TCPC_REG_PD_REV_VER_VER_MAJOR_MASK) >> 4)

Macro to extract the major part of USB Port Controller Interface version supported.

TCPC_REG_PD_INT_REV_VER_MAJOR_MASK

#define TCPC_REG_PD_INT_REV_VER_MAJOR_MASK   GENMASK(7, 4)

Mask for major part of USB Port Controller Interface version supported.

TCPC_REG_PD_INT_REV_VER_MINOR

#define TCPC_REG_PD_INT_REV_VER_MINOR

(

reg

)

Value:

((reg) & TCPC_REG_PD_REV_VER_VER_MINOR_MASK)

Macro to extract the minor part of USB Port Controller Interface version supported.

TCPC_REG_PD_INT_REV_VER_MINOR_MASK

#define TCPC_REG_PD_INT_REV_VER_MINOR_MASK   GENMASK(3, 0)

Mask for minor part of USB Port Controller Interface version supported.

TCPC_REG_PD_REV

#define TCPC_REG_PD_REV   0x8

Register address - Power delivery revision.

TCPC_REG_PD_REV_REV_MAJOR

#define TCPC_REG_PD_REV_REV_MAJOR

(

reg

)

Value:

(((reg) & TCPC_REG_PD_REV_VER_REV_MAJOR_MASK) >> 12)

Macro to extract the major part of USB PD revision supported.

TCPC_REG_PD_REV_REV_MAJOR_MASK

#define TCPC_REG_PD_REV_REV_MAJOR_MASK   GENMASK(15, 12)

Mask for major part of USB PD revision supported.

TCPC_REG_PD_REV_REV_MINOR

#define TCPC_REG_PD_REV_REV_MINOR

(

reg

)

Value:

(((reg) & TCPC_REG_PD_REV_VER_REV_MINOR_MASK) >> 8)

Macro to extract the minor part of USB PD revision supported.

TCPC_REG_PD_REV_REV_MINOR_MASK

#define TCPC_REG_PD_REV_REV_MINOR_MASK   GENMASK(11, 8)

Mask for minor part of USB PD revision supported.

TCPC_REG_PD_REV_VER_MAJOR

#define TCPC_REG_PD_REV_VER_MAJOR

(

reg

)

Value:

(((reg) & TCPC_REG_PD_REV_VER_VER_MAJOR_MASK) >> 4)

Macro to extract the major part of USB PD version supported.

TCPC_REG_PD_REV_VER_MAJOR_MASK

#define TCPC_REG_PD_REV_VER_MAJOR_MASK   GENMASK(7, 4)

Mask for major part of USB PD version supported.

TCPC_REG_PD_REV_VER_MINOR

#define TCPC_REG_PD_REV_VER_MINOR

(

reg

)

Value:

((reg) & TCPC_REG_PD_REV_VER_VER_MINOR_MASK)

Macro to extract the minor part of USB PD version supported.

TCPC_REG_PD_REV_VER_MINOR_MASK

#define TCPC_REG_PD_REV_VER_MINOR_MASK   GENMASK(3, 0)

Mask for minor part of USB PD version supported.

TCPC_REG_POWER_CTRL

#define TCPC_REG_POWER_CTRL   0x1c

Register address - power control.

TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT

#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT   BIT(4)

Bit for enabling the automatic vbus discharge based on the vbus voltage.

TCPC_REG_POWER_CTRL_BLEED_DISCHARGE

#define TCPC_REG_POWER_CTRL_BLEED_DISCHARGE   BIT(3)

Bit for enabling the bleed discharge of vbus.

TCPC_REG_POWER_CTRL_FORCE_DISCHARGE

#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE   BIT(2)

Bit for enabling the forced vbus discharge.

TCPC_REG_POWER_CTRL_FRS_ENABLE

#define TCPC_REG_POWER_CTRL_FRS_ENABLE   BIT(7)

Bit for fast role swap enable.

TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS

#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS   BIT(6)

Bit for disabling the vbus voltage monitoring.

TCPC_REG_POWER_CTRL_VCONN_EN

#define TCPC_REG_POWER_CTRL_VCONN_EN   BIT(0)

Bit for enabling the vconn sourcing to CC line.

TCPC_REG_POWER_CTRL_VCONN_SUPP

#define TCPC_REG_POWER_CTRL_VCONN_SUPP   BIT(1)

Bit for enabling the vconn power supported.

If set, the TCPC will deliver at least the power indicated in the vconn power supported in device capabilities register to the vconn. If unset, at least 1W of power will be delivered to vconn.

TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS

#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS   BIT(5)

Bit for disabling the voltage alarms.

TCPC_REG_POWER_STATUS

#define TCPC_REG_POWER_STATUS   0x1e

Register address - power status.

TCPC_REG_POWER_STATUS_DEBUG_ACC_CON

#define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON   BIT(7)

Bit for debug accessory connected.

TCPC_REG_POWER_STATUS_MASK

#define TCPC_REG_POWER_STATUS_MASK   0x14

Register address - power status mask The bits for specific masks are on the same positions as for the.

See also

TCPC_REG_POWER_STATUS register.

TCPC_REG_POWER_STATUS_SINKING_VBUS

#define TCPC_REG_POWER_STATUS_SINKING_VBUS   BIT(0)

Bit for sinking vbus.

If set, the TCPC is sinking vbus to the system load.

TCPC_REG_POWER_STATUS_SOURCING_HV

#define TCPC_REG_POWER_STATUS_SOURCING_HV   BIT(5)

Bit for sourcing high voltage.

If set, the voltage sourced is above the vSafe5V.

TCPC_REG_POWER_STATUS_SOURCING_VBUS

#define TCPC_REG_POWER_STATUS_SOURCING_VBUS   BIT(4)

Bit for sourcing vbus.

If set, sourcing vbus is enabled.

TCPC_REG_POWER_STATUS_UNINIT

#define TCPC_REG_POWER_STATUS_UNINIT   BIT(6)

Bit for internal initialization in-progress.

If set, only registers 00-0F contain valid data.

TCPC_REG_POWER_STATUS_VBUS_DET

#define TCPC_REG_POWER_STATUS_VBUS_DET   BIT(3)

Bit for vbus detection enabled.

TCPC_REG_POWER_STATUS_VBUS_PRES

#define TCPC_REG_POWER_STATUS_VBUS_PRES   BIT(2)

Bit for vbus present.

If set, the vbus shall be above 4V. If unset, the vbus shall be below 3.5V.

TCPC_REG_POWER_STATUS_VCONN_PRES

#define TCPC_REG_POWER_STATUS_VCONN_PRES   BIT(1)

Bit for vconn present.

Set if vconn is present on CC1 or CC2, threshold is fixed at 2.4V.

TCPC_REG_PRODUCT_ID

#define TCPC_REG_PRODUCT_ID   0x2

Register address - product id.

TCPC_REG_ROLE_CTRL

#define TCPC_REG_ROLE_CTRL   0x1a

Register address - role control.

TCPC_REG_ROLE_CTRL_CC1

#define TCPC_REG_ROLE_CTRL_CC1

(

reg

)

Value:

((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)

Macro to extract the enum tc_cc_pull for CC1 from register value.

TCPC_REG_ROLE_CTRL_CC1_MASK

#define TCPC_REG_ROLE_CTRL_CC1_MASK   GENMASK(1, 0)

Mask to extract the CC! pull value from register value.

TCPC_REG_ROLE_CTRL_CC2

#define TCPC_REG_ROLE_CTRL_CC2

(

reg

)

Value:

(((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)

Macro to extract the enum tc_cc_pull for CC2 from register value.

TCPC_REG_ROLE_CTRL_CC2_MASK

#define TCPC_REG_ROLE_CTRL_CC2_MASK   GENMASK(3, 2)

Mask to extract the CC2 pull value from register value.

TCPC_REG_ROLE_CTRL_DRP

#define TCPC_REG_ROLE_CTRL_DRP

(

reg

)

Value:

(((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)

TCPC_REG_ROLE_CTRL_DRP_MASK

#define TCPC_REG_ROLE_CTRL_DRP_MASK   BIT(6)

Bit for dual-role port.

TCPC_REG_ROLE_CTRL_RP

#define TCPC_REG_ROLE_CTRL_RP

(

reg

)

Value:

(((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)

Macro to extract the enum tc_rp_value from register value.

TCPC_REG_ROLE_CTRL_RP_MASK

#define TCPC_REG_ROLE_CTRL_RP_MASK   GENMASK(5, 4)

Mask to extract the RP value from register value.

TCPC_REG_ROLE_CTRL_SET

#define TCPC_REG_ROLE_CTRL_SET	(		drp,
			rp,
			cc1,
			cc2 )

Value:

        ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) |                                            \
         (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) |                                              \
         (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK))

Macro to set the register value from drp, rp and CC lines values.

TCPC_REG_RX_BUFFER

#define TCPC_REG_RX_BUFFER   0x30

Register address - receive buffer (readable byte count, rx buf frame type, rx buf byte x) In TCPC Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers: READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x.

These registers can only be accessed by reading at a common register address 30h.

TCPC_REG_RX_DETECT

#define TCPC_REG_RX_DETECT   0x2f

Register address - receive detect.

TCPC_REG_RX_DETECT_CABLE_RST

#define TCPC_REG_RX_DETECT_CABLE_RST   BIT(6)

Bit for enable cable reset.

If set, TCPC will detect the cable reset signal.

TCPC_REG_RX_DETECT_HRST

#define TCPC_REG_RX_DETECT_HRST   BIT(5)

Bit for enable hard reset.

If set, TCPC will detect the hard reset signal.

TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT

#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT   BIT(7)

Bit for message disable disconnect.

If set, the TCPC set as sink shall disable the PD message delivery when the SNK.Open state is detected for debounce time specified in specification. If unset, sink TCPC disables the PD message delivery when vbus sink disconnect detected in alert register is asserted.

TCPC_REG_RX_DETECT_SOP

#define TCPC_REG_RX_DETECT_SOP   BIT(0)

Bit for enable SOP message.

If set, TCPC will detect the SOP messages.

TCPC_REG_RX_DETECT_SOP_HRST_MASK

#define TCPC_REG_RX_DETECT_SOP_HRST_MASK   (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST)

Mask for detecting the SOP messages and hard reset signals.

TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK

#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK

Value:

        (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | TCPC_REG_RX_DETECT_SOPPP |             \
         TCPC_REG_RX_DETECT_HRST)

Mask for detecting the SOP, SOP' and SOP'' messages and hard reset signals.

TCPC_REG_RX_DETECT_SOPP

#define TCPC_REG_RX_DETECT_SOPP   BIT(1)

Bit for enable SOP' message.

If set, TCPC will detect the SOP' messages.

TCPC_REG_RX_DETECT_SOPP_DBG

#define TCPC_REG_RX_DETECT_SOPP_DBG   BIT(3)

Bit for enable SOP_DBG' message.

If set, TCPC will detect the SOP_DBG' messages.

TCPC_REG_RX_DETECT_SOPPP

#define TCPC_REG_RX_DETECT_SOPPP   BIT(2)

Bit for enable SOP'' message.

If set, TCPC will detect the SOP'' messages.

TCPC_REG_RX_DETECT_SOPPP_DBG

#define TCPC_REG_RX_DETECT_SOPPP_DBG   BIT(4)

Bit for enable SOP_DBG'' message.

If set, TCPC will detect the SOP_DBG'' messages.

TCPC_REG_STD_INPUT_CAP

#define TCPC_REG_STD_INPUT_CAP   0x28

Register address - standard input capabilities.

TCPC_REG_STD_INPUT_CAP_EXT_OCP

#define TCPC_REG_STD_INPUT_CAP_EXT_OCP   BIT(1)

Bit for vbus external over current fault.

If set, input pin is present in TCPC.

TCPC_REG_STD_INPUT_CAP_EXT_OVP

#define TCPC_REG_STD_INPUT_CAP_EXT_OVP   BIT(2)

Bit for vbus external over voltage fault.

If set, input pin is present in TCPC.

TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS

#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS   BIT(0)

Bit for force off vbus present.

If set, input pin is present in TCPC.

TCPC_REG_STD_INPUT_CAP_SRC_FRS

#define TCPC_REG_STD_INPUT_CAP_SRC_FRS

(

reg

)

Value:

(((reg) & TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK) >> 3)

Macro to extract the source fast role swap from register value.

TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK

#define TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK   GENMASK(4, 3)

Mask for source fast role swap.

TCPC_REG_STD_INTPU_CAP_SRC_FRS_BOTH

#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_BOTH   2

Value for source fast role swap both input and output pin present in TCPC.

TCPC_REG_STD_INTPU_CAP_SRC_FRS_INPUT

#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_INPUT   1

Value for source fast role swap input only pin present in TCPC.

TCPC_REG_STD_INTPU_CAP_SRC_FRS_NONE

#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_NONE   0

Value for no source fast role swap pin present in TCPC.

TCPC_REG_STD_OUTPUT_CAP

#define TCPC_REG_STD_OUTPUT_CAP   0x29

Register address - standard output capabilities.

TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE

#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE   BIT(3)

Bit for active cable indicator.

TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY

#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY   BIT(4)

Bit for audio adapter accessory indicator.

TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION

#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION   BIT(0)

Bit for connector orientation.

TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT

#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT   BIT(1)

Bit for connection present.

TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY

#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY   BIT(6)

Bit for debug accessory indicator.

TCPC_REG_STD_OUTPUT_CAP_MUX_CFG_CTRL

#define TCPC_REG_STD_OUTPUT_CAP_MUX_CFG_CTRL   BIT(2)

Bit for mux configuration control.

TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET

#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET   BIT(7)

Bit for vbus sink disconnect detect indicator.

TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON

#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON   BIT(5)

Bit for vbus present monitor.

TCPC_REG_TC_REV

#define TCPC_REG_TC_REV   0x6

Register address - USB TypeC version.

TCPC_REG_TC_REV_MAJOR

#define TCPC_REG_TC_REV_MAJOR

(

reg

)

Value:

(((reg) & TCPC_REG_TC_REV_MAJOR_MASK) >> 4)

Macro to extract the major part of type-c release supported.

TCPC_REG_TC_REV_MAJOR_MASK

#define TCPC_REG_TC_REV_MAJOR_MASK   GENMASK(7, 4)

Mask for major part of type-c release supported.

TCPC_REG_TC_REV_MINOR

#define TCPC_REG_TC_REV_MINOR

(

reg

)

Value:

((reg) & TCPC_REG_TC_REV_MINOR_MASK)

Macro to extract the minor part of type-c release supported.

TCPC_REG_TC_REV_MINOR_MASK

#define TCPC_REG_TC_REV_MINOR_MASK   GENMASK(3, 0)

Mask for minor part of type-c release supported.

TCPC_REG_TCPC_CTRL

#define TCPC_REG_TCPC_CTRL   0x19

Register address - TCPC control.

TCPC_REG_TCPC_CTRL_BIST_TEST_MODE

#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE   BIT(1)

Bit for BIST test mode enabled.

TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_DISABLED

#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_DISABLED   0

Value for clock stretching disabled.

TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_ALWAYS

#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_ALWAYS   (2 << 2)

Value for limited clock stretching enabled.

TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_NO_ALERT

#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_NO_ALERT   (3 << 2)

Value for clock stretching enabled only when alert is NOT asserted.

TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_MASK

#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_MASK   GENMASK(3, 2)

Mask.

TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL

#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL   BIT(4)

Bit for enable debug accessory control by TCPM.

TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT

#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT   BIT(6)

Bit for enabling the alert assertion when a connection is found.

TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION

#define TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION   BIT(0)

Bit for plug orientation and vconn destination.

TCPC_REG_TCPC_CTRL_SMBUS_PEC

#define TCPC_REG_TCPC_CTRL_SMBUS_PEC   BIT(7)

Bit for SMBus PEC enabled.

TCPC_REG_TCPC_CTRL_WATCHDOG_TIMER

#define TCPC_REG_TCPC_CTRL_WATCHDOG_TIMER   BIT(5)

Bit for watchdog monitoring.

TCPC_REG_TRANSMIT

#define TCPC_REG_TRANSMIT   0x50

Register address - transmit.

TCPC_REG_TRANSMIT_SET_WITH_RETRY

#define TCPC_REG_TRANSMIT_SET_WITH_RETRY	(		retries,
			type )

Value:

((retries) << 4 | (type))

Macro to set the transmit register with message type and retries count.

TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY

#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY

(

type

)

Value:

(type)

Macro to set the transmit register with message type and without retries.

TCPC_REG_TRANSMIT_TYPE_BIST

#define TCPC_REG_TRANSMIT_TYPE_BIST   7

Value for transmit BIST carrier mode 2.

TCPC_REG_TRANSMIT_TYPE_CABLE_RST

#define TCPC_REG_TRANSMIT_TYPE_CABLE_RST   6

Value for transmit cable reset signal.

TCPC_REG_TRANSMIT_TYPE_HRST

#define TCPC_REG_TRANSMIT_TYPE_HRST   5

Value for transmit hard reset signal.

TCPC_REG_TRANSMIT_TYPE_SOP

#define TCPC_REG_TRANSMIT_TYPE_SOP   0

Value for transmit SOP type message.

TCPC_REG_TRANSMIT_TYPE_SOP_DBG_P

#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_P   3

Value for transmit SOP_DBG' type message.

TCPC_REG_TRANSMIT_TYPE_SOP_DBG_PP

#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_PP   4

Value for transmit SOP_DBG'' type message.

TCPC_REG_TRANSMIT_TYPE_SOPP

#define TCPC_REG_TRANSMIT_TYPE_SOPP   1

Value for transmit SOP' type message.

TCPC_REG_TRANSMIT_TYPE_SOPPP

#define TCPC_REG_TRANSMIT_TYPE_SOPPP   2

Value for transmit SOP'' type message.

TCPC_REG_TX_BUFFER

#define TCPC_REG_TX_BUFFER   0x51

Register address - transmit buffer In TCPC Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the portion of the SOP* USB PD message payload (including the header and/or the data bytes) most recently written by the TCPM in TX_BUF_BYTE_x.

TX_BUF_BYTE_x is “hidden” and can only be accessed by writing to register address 51h

TCPC_REG_VBUS_NONDEFAULT_TARGET

#define TCPC_REG_VBUS_NONDEFAULT_TARGET   0x7a

Register address - vbus nondefault target Available only if vbus nondefault target is asserted in device capabilities 1 register.

Purpose of this register is to provide value for nondefault voltage over vbus when sending the source vbus nondefault voltage command to command register.

TCPC_REG_VBUS_NONDEFAULT_TARGET_LSB

#define TCPC_REG_VBUS_NONDEFAULT_TARGET_LSB   20

Resolution of the value stored in register.

Value read from register must be multiplied by this value to get a real voltage in mV. Voltage in mV written to register must be divided by this constant. Specification defines it as 20mV

TCPC_REG_VBUS_SINK_DISCONNECT_THRESH

#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH   0x72

Register address - vbus sink disconnect threshold.

TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT

#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT   0x008C /* 3.5 V */

Default value for vbus sink disconnect threshold.

TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_LSB

#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_LSB   25

Resolution of the value stored in register.

Value read from register must be multiplied by this value to get a real voltage in mV. Voltage in mV written to register must be divided by this constant. Specification defines it as 25mV

TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_MASK

#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_MASK   GENMASK(11, 0)

Mask for the valid bits of voltage trip point.

TCPC_REG_VBUS_STOP_DISCHARGE_THRESH

#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH   0x74

Register address - vbus sink disconnect threshold.

TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_DEFAULT

#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_DEFAULT   0x0020 /* 0.8 V */

Default value for vbus stop discharge threshold.

TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_LSB

#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_LSB   25

Resolution of the value stored in register.

Value read from register must be multiplied by this value to get a real voltage in mV. Voltage in mV written to register must be divided by this constant. Specification defines it as 25mV.

TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_MASK

#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_MASK   GENMASK(11, 0)

Mask for the valid bits of voltage trip point.

TCPC_REG_VBUS_VOLTAGE

#define TCPC_REG_VBUS_VOLTAGE   0x70

Register address - vbus voltage.

TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG

#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG   0x76

Register address - vbus voltage alarm - high.

TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_LSB

#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_LSB   25

Resolution of the value stored in register.

Value read from register must be multiplied by this value to get a real voltage in mV. Voltage in mV written to register must be divided by this constant. Specification defines it as 25mV

TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_MASK

#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_MASK   GENMASK(11, 0)

Mask for the valid bits of voltage trip point.

TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG

#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG   0x78

Register address - vbus voltage alarm - low.

TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_LSB

#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_LSB   25

Resolution of the value stored in register.

Value read from register must be multiplied by this value to get a real voltage in mV. Voltage in mV written to register must be divided by this constant. Specification defines it as 25mV

TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_MASK

#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_MASK   GENMASK(11, 0)

Mask for the valid bits of voltage trip point.

TCPC_REG_VBUS_VOLTAGE_LSB

#define TCPC_REG_VBUS_VOLTAGE_LSB   25

Resolution of vbus voltage measurement.

It's specified as 25mV.

TCPC_REG_VBUS_VOLTAGE_MEASUREMENT

#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT

(

reg

)

Value:

((reg) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK)

Macro to extract the vbus measurement from the register value.

TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK

#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK   GENMASK(9, 0)

Mask for vbus voltage measurement.

TCPC_REG_VBUS_VOLTAGE_SCALE

#define TCPC_REG_VBUS_VOLTAGE_SCALE

(

reg

)

Value:

        (1 << (((reg) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK) >> 10))

Macro to extract the vbus voltage scale from the register value.

TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK

#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK   GENMASK(11, 10)

Mask for scale factor.

TCPC_REG_VBUS_VOLTAGE_VBUS

#define TCPC_REG_VBUS_VOLTAGE_VBUS

(

x

)

Value:

        (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(x) *                   \
         TCPC_REG_VBUS_VOLTAGE_LSB)

Macro to convert the register value into real voltage measurement taking scale factor into account.

TCPC_REG_VENDOR_ID

#define TCPC_REG_VENDOR_ID   0x0

Register address - vendor id.