9#ifndef _TEST_ASM_INLINE_GCC_H
10#define _TEST_ASM_INLINE_GCC_H
15#error test_asm_inline_gcc.h goes only with GCC
18#if defined(CONFIG_X86)
21 __asm__ __volatile__ (
22 "xorl %%eax,%%eax;\n\t"
26 :
"%eax",
"%ebx",
"%ecx",
"%edx");
28#elif defined(CONFIG_CPU_CORTEX_M) || \
29 defined(CONFIG_CPU_AARCH32_CORTEX_R) || \
30 defined(CONFIG_CPU_AARCH32_CORTEX_A) || \
31 defined(CONFIG_CPU_CORTEX_A) || \
32 defined(CONFIG_CPU_AARCH64_CORTEX_R)
37#elif defined(CONFIG_ARC)
38#define timestamp_serialize()
39#elif defined(CONFIG_ARCH_POSIX)
40#define timestamp_serialize()
41#elif defined(CONFIG_XTENSA)
42#define timestamp_serialize()
43#elif defined(CONFIG_RISCV)
44#define timestamp_serialize()
45#elif defined(CONFIG_SPARC)
46#define timestamp_serialize()
47#elif defined(CONFIG_MIPS)
48#define timestamp_serialize()
49#elif defined(CONFIG_RX)
50#define timestamp_serialize()
52#error implementation of timestamp_serialize() not provided for your CPU target
static ALWAYS_INLINE void barrier_isync_fence_full(void)
Full/sequentially-consistent instruction synchronization barrier.
Definition barrier.h:78
static void timestamp_serialize(void)
Definition test_asm_inline_other.h:15