Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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ti_dmtimer.h
Go to the documentation of this file.
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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
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#define ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
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#include <
zephyr/devicetree.h
>
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#define TI_DM_TIMER_TIDR (0x00)
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#define TI_DM_TIMER_TIOCP_CFG (0x10)
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#define TI_DM_TIMER_IRQ_EOI (0x20)
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#define TI_DM_TIMER_IRQSTATUS_RAW (0x24)
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#define TI_DM_TIMER_IRQSTATUS (0x28)
/* Interrupt status register */
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#define TI_DM_TIMER_IRQENABLE_SET (0x2c)
/* Interrupt enable register */
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#define TI_DM_TIMER_IRQENABLE_CLR (0x30)
/* Interrupt disable register */
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#define TI_DM_TIMER_IRQWAKEEN (0x34)
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#define TI_DM_TIMER_TCLR (0x38)
/* Control register */
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#define TI_DM_TIMER_TCRR (0x3c)
/* Counter register */
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#define TI_DM_TIMER_TLDR (0x40)
/* Load register */
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#define TI_DM_TIMER_TTGR (0x44)
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#define TI_DM_TIMER_TWPS (0x48)
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#define TI_DM_TIMER_TMAR (0x4c)
/* Match register */
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#define TI_DM_TIMER_TCAR1 (0x50)
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#define TI_DM_TIMER_TSICR (0x54)
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#define TI_DM_TIMER_TCAR2 (0x58)
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#define TI_DM_TIMER_TPIR (0x5c)
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#define TI_DM_TIMER_TNIR (0x60)
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#define TI_DM_TIMER_TCVR (0x64)
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#define TI_DM_TIMER_TOCR (0x68)
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#define TI_DM_TIMER_TOWR (0x6c)
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#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT (0)
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#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_MASK (0x00000001)
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#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_SHIFT (1)
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#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_MASK (0x00000002)
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#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_SHIFT (2)
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#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_MASK (0x00000004)
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#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_SHIFT (0)
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#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_MASK (0x00000001)
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#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_SHIFT (1)
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#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_MASK (0x00000002)
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#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_SHIFT (2)
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#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_MASK (0x00000004)
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#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_SHIFT (0)
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#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_MASK (0x00000001)
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#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_SHIFT (1)
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#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_MASK (0x00000002)
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#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_SHIFT (2)
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#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_MASK (0x00000004)
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#define TI_DM_TIMER_TCLR_ST_SHIFT (0)
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#define TI_DM_TIMER_TCLR_ST_MASK (0x00000001)
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#define TI_DM_TIMER_TCLR_AR_SHIFT (1)
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#define TI_DM_TIMER_TCLR_AR_MASK (0x00000002)
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#define TI_DM_TIMER_TCLR_PTV_SHIFT (2)
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#define TI_DM_TIMER_TCLR_PTV_MASK (0x0000001c)
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#define TI_DM_TIMER_TCLR_PRE_SHIFT (5)
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#define TI_DM_TIMER_TCLR_PRE_MASK (0x00000020)
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#define TI_DM_TIMER_TCLR_CE_SHIFT (6)
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#define TI_DM_TIMER_TCLR_CE_MASK (0x00000040)
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#define TI_DM_TIMER_TCLR_SCPWM_SHIFT (7)
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#define TI_DM_TIMER_TCLR_SCPWM_MASK (0x00000080)
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#define TI_DM_TIMER_TCLR_TCM_SHIFT (8)
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#define TI_DM_TIMER_TCLR_TCM_MASK (0x00000300)
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#define TI_DM_TIMER_TCLR_TRG_SHIFT (10)
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#define TI_DM_TIMER_TCLR_TRG_MASK (0x00000c00)
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#define TI_DM_TIMER_TCLR_PT_SHIFT (12)
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#define TI_DM_TIMER_TCLR_PT_MASK (0x00001000)
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#define TI_DM_TIMER_TCLR_CAPT_MODE_SHIFT (13)
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#define TI_DM_TIMER_TCLR_CAPT_MODE_MASK (0x00002000)
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#define TI_DM_TIMER_TCLR_GPO_CFG_SHIFT (14)
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#define TI_DM_TIMER_TCLR_GPO_CFG_MASK (0x00004000)
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#define TI_DM_TIMER_TCRR_TIMER_COUNTER_SHIFT (0)
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#define TI_DM_TIMER_TCRR_TIMER_COUNTER_MASK (0xffffffff)
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#define TI_DM_TIMER_TLDR_LOAD_VALUE_SHIFT (0)
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#define TI_DM_TIMER_TLDR_LOAD_VALUE_MASK (0xffffffff)
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#define TI_DM_TIMER_TMAR_COMPARE_VALUE_SHIFT (0)
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#define TI_DM_TIMER_TMAR_COMPARE_VALUE_MASK (0xffffffff)
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#endif
/* ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_ */
devicetree.h
Devicetree main header.
zephyr
drivers
timer
ti_dmtimer.h
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