Zephyr API Documentation
3.7.0
A Scalable Open Source RTOS
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MSPI controller device specific configuration. More...
#include <mspi.h>
Data Fields | |
uint8_t | ce_num |
Configure CE0 or CE1 or more. | |
uint32_t | freq |
Configure frequency. | |
enum mspi_io_mode | io_mode |
Configure I/O mode. | |
enum mspi_data_rate | data_rate |
Configure data rate. | |
enum mspi_cpp_mode | cpp |
Configure clock polarity and phase. | |
enum mspi_endian | endian |
Configure transfer endian. | |
enum mspi_ce_polarity | ce_polarity |
Configure chip enable polarity. | |
bool | dqs_enable |
Configure DQS mode. | |
uint16_t | rx_dummy |
Configure number of clock cycles between addr and data in RX direction. | |
uint16_t | tx_dummy |
Configure number of clock cycles between addr and data in TX direction. | |
uint32_t | read_cmd |
Configure read command | |
uint32_t | write_cmd |
Configure write command | |
uint8_t | cmd_length |
Configure command length | |
uint8_t | addr_length |
Configure address length | |
uint32_t | mem_boundary |
Configure memory boundary | |
uint32_t | time_to_break |
Configure the time to break up a transfer into 2. | |
MSPI controller device specific configuration.
uint8_t mspi_dev_cfg::addr_length |
Configure address length
uint8_t mspi_dev_cfg::ce_num |
Configure CE0 or CE1 or more.
enum mspi_ce_polarity mspi_dev_cfg::ce_polarity |
Configure chip enable polarity.
uint8_t mspi_dev_cfg::cmd_length |
Configure command length
enum mspi_cpp_mode mspi_dev_cfg::cpp |
Configure clock polarity and phase.
enum mspi_data_rate mspi_dev_cfg::data_rate |
Configure data rate.
bool mspi_dev_cfg::dqs_enable |
Configure DQS mode.
enum mspi_endian mspi_dev_cfg::endian |
Configure transfer endian.
uint32_t mspi_dev_cfg::freq |
Configure frequency.
enum mspi_io_mode mspi_dev_cfg::io_mode |
Configure I/O mode.
uint32_t mspi_dev_cfg::mem_boundary |
Configure memory boundary
uint32_t mspi_dev_cfg::read_cmd |
Configure read command
uint16_t mspi_dev_cfg::rx_dummy |
Configure number of clock cycles between addr and data in RX direction.
uint32_t mspi_dev_cfg::time_to_break |
Configure the time to break up a transfer into 2.
uint16_t mspi_dev_cfg::tx_dummy |
Configure number of clock cycles between addr and data in TX direction.
uint32_t mspi_dev_cfg::write_cmd |
Configure write command