Macros
#define	MAX32_DMA_SLOT_MEMTOMEM 0x00U

#define	MAX32_DMA_SLOT_SPI0_RX 0x01U

#define	MAX32_DMA_SLOT_SPI1_RX 0x02U

#define	MAX32_DMA_SLOT_UART0_RX 0x04U

#define	MAX32_DMA_SLOT_I2C0_RX 0x07U

#define	MAX32_DMA_SLOT_I2C2_RX 0x0AU

#define	MAX32_DMA_SLOT_UART2_RX 0x0EU

#define	MAX32_DMA_SLOT_AES_RX 0x10U

#define	MAX32_DMA_SLOT_I2S_RX 0x1EU

#define	MAX32_DMA_SLOT_SPI0_TX 0x21U

#define	MAX32_DMA_SLOT_SPI1_TX 0x22U

#define	MAX32_DMA_SLOT_UART0_TX 0x24U

#define	MAX32_DMA_SLOT_I2C0_TX 0x27U

#define	MAX32_DMA_SLOT_I2C2_TX 0x2AU

#define	MAX32_DMA_SLOT_CRC 0x2CU

#define	MAX32_DMA_SLOT_UART2_TX 0x2EU

#define	MAX32_DMA_SLOT_AES_TX 0x30U

#define	MAX32_DMA_SLOT_I2S_TX 0x3EU

Macro Definition Documentation

◆ MAX32_DMA_SLOT_AES_RX

#define MAX32_DMA_SLOT_AES_RX 0x10U

◆ MAX32_DMA_SLOT_AES_TX

#define MAX32_DMA_SLOT_AES_TX 0x30U

◆ MAX32_DMA_SLOT_CRC

#define MAX32_DMA_SLOT_CRC 0x2CU

◆ MAX32_DMA_SLOT_I2C0_RX

#define MAX32_DMA_SLOT_I2C0_RX 0x07U

◆ MAX32_DMA_SLOT_I2C0_TX

#define MAX32_DMA_SLOT_I2C0_TX 0x27U

◆ MAX32_DMA_SLOT_I2C2_RX

#define MAX32_DMA_SLOT_I2C2_RX 0x0AU

◆ MAX32_DMA_SLOT_I2C2_TX

#define MAX32_DMA_SLOT_I2C2_TX 0x2AU

◆ MAX32_DMA_SLOT_I2S_RX

#define MAX32_DMA_SLOT_I2S_RX 0x1EU

◆ MAX32_DMA_SLOT_I2S_TX

#define MAX32_DMA_SLOT_I2S_TX 0x3EU

◆ MAX32_DMA_SLOT_MEMTOMEM

#define MAX32_DMA_SLOT_MEMTOMEM 0x00U

◆ MAX32_DMA_SLOT_SPI0_RX

#define MAX32_DMA_SLOT_SPI0_RX 0x01U

◆ MAX32_DMA_SLOT_SPI0_TX

#define MAX32_DMA_SLOT_SPI0_TX 0x21U

◆ MAX32_DMA_SLOT_SPI1_RX

#define MAX32_DMA_SLOT_SPI1_RX 0x02U

◆ MAX32_DMA_SLOT_SPI1_TX

#define MAX32_DMA_SLOT_SPI1_TX 0x22U

◆ MAX32_DMA_SLOT_UART0_RX

#define MAX32_DMA_SLOT_UART0_RX 0x04U

◆ MAX32_DMA_SLOT_UART0_TX

#define MAX32_DMA_SLOT_UART0_TX 0x24U

◆ MAX32_DMA_SLOT_UART2_RX

#define MAX32_DMA_SLOT_UART2_RX 0x0EU

◆ MAX32_DMA_SLOT_UART2_TX

#define MAX32_DMA_SLOT_UART2_TX 0x2EU

Macros