Zephyr API Documentation 4.0.99
A Scalable Open Source RTOS
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Macros
stm32u5_clock.h File Reference
#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)
 Domain clocks.
 
#define STM32_SRC_HSI16   (STM32_SRC_HSE + 1)
 
#define STM32_SRC_HSI48   (STM32_SRC_HSI16 + 1)
 
#define STM32_SRC_MSIS   (STM32_SRC_HSI48 + 1)
 
#define STM32_SRC_MSIK   (STM32_SRC_MSIS + 1)
 
#define STM32_SRC_HCLK   (STM32_SRC_MSIK + 1)
 Bus clock.
 
#define STM32_SRC_PCLK1   (STM32_SRC_HCLK + 1)
 
#define STM32_SRC_PCLK2   (STM32_SRC_PCLK1 + 1)
 
#define STM32_SRC_PCLK3   (STM32_SRC_PCLK2 + 1)
 
#define STM32_SRC_PLL1_P   (STM32_SRC_PCLK3 + 1)
 PLL outputs.
 
#define STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)
 
#define STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)
 
#define STM32_SRC_PLL2_P   (STM32_SRC_PLL1_R + 1)
 
#define STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)
 
#define STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)
 
#define STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)
 
#define STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)
 
#define STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)
 
#define STM32_CLOCK_BUS_AHB1   0x088
 Clock muxes.
 
#define STM32_CLOCK_BUS_AHB2   0x08C
 
#define STM32_CLOCK_BUS_AHB2_2   0x090
 
#define STM32_CLOCK_BUS_AHB3   0x094
 
#define STM32_CLOCK_BUS_APB1   0x09C
 
#define STM32_CLOCK_BUS_APB1_2   0x0A0
 
#define STM32_CLOCK_BUS_APB2   0x0A4
 
#define STM32_CLOCK_BUS_APB3   0x0A8
 
#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
 
#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
 
#define STM32_CLOCK_REG_MASK   0xFFU
 
#define STM32_CLOCK_REG_SHIFT   0U
 
#define STM32_CLOCK_SHIFT_MASK   0x1FU
 
#define STM32_CLOCK_SHIFT_SHIFT   8U
 
#define STM32_CLOCK_MASK_MASK   0x7U
 
#define STM32_CLOCK_MASK_SHIFT   13U
 
#define STM32_CLOCK_VAL_MASK   0x7U
 
#define STM32_CLOCK_VAL_SHIFT   16U
 
#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)
 STM32U5 clock configuration bit field.
 
#define CCIPR1_REG   0xE0
 RCC_CCIPRx register offset (RM0456.pdf)
 
#define CCIPR2_REG   0xE4
 
#define CCIPR3_REG   0xE8
 
#define BDCR_REG   0xF0
 RCC_BDCR register offset.
 
#define CFGR1_REG   0x1C
 RCC_CFGRx register offset.
 
#define USART1_SEL(val)
 Device domain clocks selection helpers.
 
#define USART2_SEL(val)
 
#define USART3_SEL(val)
 
#define UART4_SEL(val)
 
#define UART5_SEL(val)
 
#define I2C1_SEL(val)
 
#define I2C2_SEL(val)
 
#define I2C4_SEL(val)
 
#define SPI2_SEL(val)
 
#define LPTIM2_SEL(val)
 
#define SPI1_SEL(val)
 
#define SYSTICK_SEL(val)
 
#define FDCAN1_SEL(val)
 
#define ICKLK_SEL(val)
 
#define TIMIC_SEL(val)
 
#define MDF1_SEL(val)
 CCIPR2 devices.
 
#define SAI1_SEL(val)
 
#define SAI2_SEL(val)
 
#define SAE_SEL(val)
 
#define RNG_SEL(val)
 
#define SDMMC_SEL(val)
 
#define DSIHOST_SEL(val)
 
#define USART6_SEL(val)
 
#define LTDC_SEL(val)
 
#define OCTOSPI_SEL(val)
 
#define HSPI_SEL(val)
 
#define I2C5_SEL(val)
 
#define I2C6_SEL(val)
 
#define OTGHS_SEL(val)
 
#define LPUART1_SEL(val)
 CCIPR3 devices.
 
#define SPI3_SEL(val)
 
#define I2C3_SEL(val)
 
#define LPTIM34_SEL(val)
 
#define LPTIM1_SEL(val)
 
#define ADCDAC_SEL(val)
 
#define DAC1_SEL(val)
 
#define ADF1_SEL(val)
 
#define RTC_SEL(val)
 BDCR devices.
 
#define MCO1_SEL(val)
 CFGR1 devices.
 
#define MCO1_PRE(val)
 
#define MCO_PRE_DIV_1   0
 
#define MCO_PRE_DIV_2   1
 
#define MCO_PRE_DIV_4   2
 
#define MCO_PRE_DIV_8   3
 
#define MCO_PRE_DIV_16   4
 

Macro Definition Documentation

◆ ADCDAC_SEL

#define ADCDAC_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG)
STM32_DOMAIN_CLOCK
#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)
STM32U5 clock configuration bit field.
Definition stm32u5_clock.h:77
CCIPR3_REG
#define CCIPR3_REG
Definition stm32u5_clock.h:86

◆ ADF1_SEL

#define ADF1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR3_REG)

◆ BDCR_REG

#define BDCR_REG   0xF0

RCC_BDCR register offset.

◆ CCIPR1_REG

#define CCIPR1_REG   0xE0

RCC_CCIPRx register offset (RM0456.pdf)

◆ CCIPR2_REG

#define CCIPR2_REG   0xE4

◆ CCIPR3_REG

#define CCIPR3_REG   0xE8

◆ CFGR1_REG

#define CFGR1_REG   0x1C

RCC_CFGRx register offset.

◆ DAC1_SEL

#define DAC1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR3_REG)

◆ DSIHOST_SEL

#define DSIHOST_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR2_REG)
CCIPR2_REG
#define CCIPR2_REG
Definition stm32u5_clock.h:85

◆ FDCAN1_SEL

#define FDCAN1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR1_REG)
CCIPR1_REG
#define CCIPR1_REG
RCC_CCIPRx register offset (RM0456.pdf)
Definition stm32u5_clock.h:84

◆ HSPI_SEL

#define HSPI_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG)

◆ I2C1_SEL

#define I2C1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)

◆ I2C2_SEL

#define I2C2_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG)

◆ I2C3_SEL

#define I2C3_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG)

◆ I2C4_SEL

#define I2C4_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG)

◆ I2C5_SEL

#define I2C5_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG)

◆ I2C6_SEL

#define I2C6_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG)

◆ ICKLK_SEL

#define ICKLK_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR1_REG)

◆ LPTIM1_SEL

#define LPTIM1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG)

◆ LPTIM2_SEL

#define LPTIM2_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG)

◆ LPTIM34_SEL

#define LPTIM34_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR3_REG)

◆ LPUART1_SEL

#define LPUART1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG)

CCIPR3 devices.

◆ LTDC_SEL

#define LTDC_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 18, CCIPR2_REG)

◆ MCO1_PRE

#define MCO1_PRE ( val)
Value:
STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
STM32_MCO_CFGR
#define STM32_MCO_CFGR(val, mask, shift, reg)
STM32 MCO configuration register bit field.
Definition stm32_common_clocks.h:47
CFGR1_REG
#define CFGR1_REG
RCC_CFGRx register offset.
Definition stm32u5_clock.h:92

◆ MCO1_SEL

#define MCO1_SEL ( val)
Value:
STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)

CFGR1 devices.

◆ MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

◆ MCO_PRE_DIV_16

#define MCO_PRE_DIV_16   4

◆ MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   1

◆ MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   2

◆ MCO_PRE_DIV_8

#define MCO_PRE_DIV_8   3

◆ MDF1_SEL

#define MDF1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG)

CCIPR2 devices.

◆ OCTOSPI_SEL

#define OCTOSPI_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)

◆ OTGHS_SEL

#define OTGHS_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG)

◆ RNG_SEL

#define RNG_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)

◆ RTC_SEL

#define RTC_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
BDCR_REG
#define BDCR_REG
RCC_BDCR register offset.
Definition stm32u5_clock.h:89

BDCR devices.

◆ SAE_SEL

#define SAE_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 11, CCIPR2_REG)

◆ SAI1_SEL

#define SAI1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG)

◆ SAI2_SEL

#define SAI2_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG)

◆ SDMMC_SEL

#define SDMMC_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG)

◆ SPI1_SEL

#define SPI1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG)

◆ SPI2_SEL

#define SPI2_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG)

◆ SPI3_SEL

#define SPI3_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG)

◆ STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x088

Clock muxes.

Bus clocks

◆ STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x08C

◆ STM32_CLOCK_BUS_AHB2_2

#define STM32_CLOCK_BUS_AHB2_2   0x090

◆ STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x094

◆ STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x09C

◆ STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x0A0

◆ STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x0A4

◆ STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0A8

◆ STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

◆ STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

◆ STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

◆ STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

◆ STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

◆ STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

◆ STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

◆ STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

◆ STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK ( val,
mask,
shift,
reg )
Value:
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
STM32_CLOCK_SHIFT_SHIFT
#define STM32_CLOCK_SHIFT_SHIFT
Definition stm32u5_clock.h:58
STM32_CLOCK_REG_SHIFT
#define STM32_CLOCK_REG_SHIFT
Definition stm32u5_clock.h:56
STM32_CLOCK_REG_MASK
#define STM32_CLOCK_REG_MASK
Definition stm32u5_clock.h:55
STM32_CLOCK_MASK_MASK
#define STM32_CLOCK_MASK_MASK
Definition stm32u5_clock.h:59
STM32_CLOCK_VAL_MASK
#define STM32_CLOCK_VAL_MASK
Definition stm32u5_clock.h:61
STM32_CLOCK_MASK_SHIFT
#define STM32_CLOCK_MASK_SHIFT
Definition stm32u5_clock.h:60
STM32_CLOCK_VAL_SHIFT
#define STM32_CLOCK_VAL_SHIFT
Definition stm32u5_clock.h:62
STM32_CLOCK_SHIFT_MASK
#define STM32_CLOCK_SHIFT_MASK
Definition stm32u5_clock.h:57

STM32U5 clock configuration bit field.

  • reg (1/2/3) [ 0 : 7 ]
  • shift (0..31) [ 8 : 12 ]
  • mask (0x1, 0x3, 0x7) [ 13 : 15 ]
  • val (0..7) [ 16 : 18 ]
Parameters
regRCC_CCIPRx register offset
shiftPosition within RCC_CCIPRx.
maskMask for the RCC_CCIPRx field.
valClock value (0, 1, ... 7).

◆ STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

◆ STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

◆ STM32_SRC_HCLK

#define STM32_SRC_HCLK   (STM32_SRC_MSIK + 1)

Bus clock.

◆ STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

◆ STM32_SRC_HSI16

#define STM32_SRC_HSI16   (STM32_SRC_HSE + 1)

◆ STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSI16 + 1)

◆ STM32_SRC_MSIK

#define STM32_SRC_MSIK   (STM32_SRC_MSIS + 1)

◆ STM32_SRC_MSIS

#define STM32_SRC_MSIS   (STM32_SRC_HSI48 + 1)

◆ STM32_SRC_PCLK1

#define STM32_SRC_PCLK1   (STM32_SRC_HCLK + 1)

◆ STM32_SRC_PCLK2

#define STM32_SRC_PCLK2   (STM32_SRC_PCLK1 + 1)

◆ STM32_SRC_PCLK3

#define STM32_SRC_PCLK3   (STM32_SRC_PCLK2 + 1)

◆ STM32_SRC_PLL1_P

#define STM32_SRC_PLL1_P   (STM32_SRC_PCLK3 + 1)

PLL outputs.

◆ STM32_SRC_PLL1_Q

#define STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)

◆ STM32_SRC_PLL1_R

#define STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)

◆ STM32_SRC_PLL2_P

#define STM32_SRC_PLL2_P   (STM32_SRC_PLL1_R + 1)

◆ STM32_SRC_PLL2_Q

#define STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)

◆ STM32_SRC_PLL2_R

#define STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)

◆ STM32_SRC_PLL3_P

#define STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)

◆ STM32_SRC_PLL3_Q

#define STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)

◆ STM32_SRC_PLL3_R

#define STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)

◆ SYSTICK_SEL

#define SYSTICK_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG)

◆ TIMIC_SEL

#define TIMIC_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 7, 29, CCIPR1_REG)

◆ UART4_SEL

#define UART4_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG)

◆ UART5_SEL

#define UART5_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG)

◆ USART1_SEL

#define USART1_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)

Device domain clocks selection helpers.

CCIPR1 devices

◆ USART2_SEL

#define USART2_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)

◆ USART3_SEL

#define USART3_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG)

◆ USART6_SEL

#define USART6_SEL ( val)
Value:
STM32_DOMAIN_CLOCK(val, 1, 16, CCIPR2_REG)