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microchip,mcp251xfd (on spi bus)

Vendor: Microchip Technology Inc.

Description

Microchip MCP251XFD SPI CAN FD controller

The MCP251XFD node is defined on an SPI bus. An example
configuration is:

&mikrobus_spi {
    cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>;

    mcp2518fd_mikroe_mcp2518fd_click: mcp2518fd@0 {
        compatible = "microchip,mcp251xfd";
        status = "okay";

        spi-max-frequency = <18000000>;
        int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>;
        reg = <0x0>;
        osc-freq = <40000000>;

        bus-speed = <125000>;
        sample-point = <875>;
        bus-speed-data = <1000000>;
        sample-point-data = <875>;
    };
};

Properties

Top level properties

These property descriptions apply to “microchip,mcp251xfd” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

Name

Type

Details

osc-freq

int

Frequency of the external oscillator in Hz.

This property is required.

int-gpios

phandle-array

The interrupt signal from the controller is active low in push-pull mode.
The property value should ensure the flags properly describe the signal
that is presented to the driver.

This property is required.

pll-enable

boolean

Enables controller PLL, which multiplies input clock frequency by 10.
This parameter also implicitly sets whether the clock is from the PLL
output or directly from the oscillator.
If this option is enabled the clock source is the PLL, otherwise its
the oscillator.

timestamp-prescaler

int

Prescaler value for computing the timestamps of received messages.
The timestamp counter is derived from the internal clock divided by this value.
Valid range is [1, 1024].

Default value: 1

sof-on-clko

boolean

Output start-of-frame (SOF) signal on the CLKO pin every time
a Start bit of a CAN message is transmitted or received. If this option
is not set, then an internal clock (typically 40MHz or 20MHz) will be
output on CLKO pin instead.

clko-div

int

The factor to divide the system clock for CLKO pin.

Default value: 10

Legal values: 1, 2, 4, 10

spi-max-frequency

int

Maximum clock frequency of device's SPI interface in Hz

This property is required.

duplex

int

Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

Legal values: 0, 2048

frame-format

int

Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0     SPI_FRAME_FORMAT_MOTOROLA
  32768 SPI_FRAME_FORMAT_TI

Legal values: 0, 32768

spi-cpol

boolean

SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.

spi-cpha

boolean

SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.

spi-hold-cs

boolean

In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.

supply-gpios

phandle-array

GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

vin-supply

phandle

Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

bus-speed-data

int

Initial data phase bitrate in bit/s.

This property is required.

sample-point-data

int

Initial data phase sample point in per mille (e.g. 875 equals 87.5%).

This property is required unless the timing is specified using time quanta based properties
(`sjw-data`, `prop-seg-data`, `phase-seg1-data`, and `phase-seg2-data`).

If this property is present, the time quanta based timing properties are ignored.

tx-delay-comp-offset

int

bus-speed

int

Initial bitrate in bit/s.

This property is required.

sample-point

int

Initial sample point in per mille (e.g. 875 equals 87.5%).

This property is required unless the timing is specified using time quanta based properties
(`sjw`, `prop-seg`, `phase-seg1`, and `phase-seg2`).

If this property is present, the time quanta based timing properties are ignored.

phys

phandle

Actively controlled CAN transceiver.

Example:
  transceiver0: can-phy0 {
    compatible = "nxp,tja1040", "can-transceiver-gpio";
    standby-gpios = <gpioa 0 GPIO_ACTIVE_HIGH>;
    max-bitrate = <1000000>;
    #phy-cells = <0>;
  };

  &can0 {
    status = "okay";

    phys = <&transceiver0>;
  };

Child node properties

Name

Type

Details

max-bitrate

int

The maximum bitrate supported by the CAN transceiver in bits/s.

This property is required.