aesc,clock-controller

Description

Aesc Silicon Clock Controller

Clock controller for the ElemRV platform. Each clock domain exposes a control
register (enable + lock status) and a ratio register (multiplier / divider).
The output rate of a domain is computed as

    rate = reference * mult / div

where the reference clock frequency is read from the syscon device referenced
by the "syscon" property.

The clock specifier is the zero-based domain index, e.g. HYDROGEN_CLK_SYSTEM.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

syscon

phandle

Reference to the syscon node that publishes the reference clock
frequency (in Hz) used to compute each domain's rate.

This property is required.

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

Constant value: 1

Specifier cell names

  • clock cells: domain