bflb,bl61x-root-clk

Description

The BL61x Root Clock
Represents both FCLK and HCLK, which should be kept the same.
Source -> FCLK / divider -> HCLK / divider -> BCLK

'clocks' take the form of:
clocks = <&clk_wifipll BL61X_WIFIPLL_320MHz>;
Where the phandle is one of clk_wifipll, clk_aupll (Unsupported), clk_crystal, or clk_rc32m.
The second argument is from include/zephyr/dt-bindings/clock/bflb_bl61x_clock.h

Properties

Properties not inherited from the base binding file.

Name

Type

Details

divider

int

Divide source clock by this 8-bits value (FCLK divider). Typically 1.

This property is required.

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.