bflb,root-clk

Description

Bouffalolab Root Clock
Represents both FCLK and HCLK depending on their presence, which should be kept the same.
Source -> / divider -> This Clock
Please refer to the SoC datasheet's clock diagram for more details

Examples

&clk_root {
  clocks = <&clk_pll BL60X_PLL_ID_DIV5_3>;
  divider = <1>;
};

&clk_root {
  clocks = <&clk_wifipll BL61X_WIFIPLL_ID_DIV1>;
  divider = <1>;
};

&clk_root {
  clocks = <&clk_crystal>;
  divider = <1>;
};

&clk_root {
  clocks = <&clk_rc32m>;
  divider = <1>;
};

Properties

Properties not inherited from the base binding file.

Name

Type

Details

divider

int

 
Divide source clock by this 8-bits value. Typically 1.

This property is required.

#clock-cells

int

 
Number of items to expect in a Clock specifier

This property is required.