microchip,sam-d5x-e5x-dfll

Description

SAM_D5x_E5x Internal Oscillator (OSC48M)

Digital Frequency-Locked Loop (DFLL48M) configuration.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

dfll-on-demand-en

int

0: The oscillator is always on
1: The oscillator is running when a peripheral is requesting the oscillator to be used as a
clock source. The oscillator is not running if no peripheral is requesting the clock source.
Important: Initializing it with 1, along with clock enabled, can lead to indefinite wait for
the clock to be on, if there is no peripheral request for the clock in the sequence of clock
Initialization. If required, better to turn on the clock using API, instead of enabling both
during startup.

Legal values: 0, 1

dfll-run-in-standby-en

int

0: The DFLL is not running in standby sleep mode if no peripheral requests the clock.
1: The DFLL is running in standby sleep mode.
If ONDEMAND is one, the DFLL will be running when a peripheral is requesting the clock. If
ONDEMAND is false, the clock source will always be running in standby sleep mode.

Legal values: 0, 1

dfll-en

int

Oscillator Enable
0: to disable, 1: to enable

Default value: 1

Legal values: 0, 1

dfll-wait-lock-en

int

If enabled, clock available only after DFLL is locked (Fine lock)
0: to disable, 1: to enable

Legal values: 0, 1

dfll-bypass-coarse-lock-en

int

To bypass coarse lock procedure
0: to disable, 1: to enable

Legal values: 0, 1

dfll-quick-lock-dis

int

Disable quick lock
1: to disable, 0: to enable

Legal values: 0, 1

dfll-chill-cycle-dis

int

Disable chill cycle
1: to disable, 0: to enable

The time from selecting a new CLK_DFLL48M frequency until this frequency is output
by the DFLL48M can be up to several microseconds. If the value of dfll-multiply-factor
is small, this can lead to instability in the DFLL48M locking mechanism, which can prevent
the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the CLK_DFLL48M
frequency is not measured, can be enabled. Enabling chill cycles might double the lock time.

Legal values: 0, 1

dfll-usb-recovery-en

int

Enable USB Clock Recovery Mode
0: to disable, 1: to enable

Legal values: 0, 1

dfll-lose-lock-en

int

If enabled, locks will be lost after waking up from sleep modes,
if the DFLL clock has been stopped
0: Locks will not be lost after waking up from sleep modes
1: Locks will be lost after waking up from sleep modes

Legal values: 0, 1

dfll-stable-freq-en

int

0: FINE calibration tracks changes in output frequency.
1: FINE calibration register value will be fixed after a fine lock.

Legal values: 0, 1

dfll-closed-loop-en

int

0: The DFLL operates in open-loop operation.
1: The DFLL operates in closed-loop operation.

Legal values: 0, 1

dfll-coarse-max-step

int

Indicates the maximum step size allowed during coarse adjustment in closed-loop mode (0 - 31)

dfll-fine-max-step

int

Indicates the maximum step size allowed during fine adjustment in closed-loop mode (0 - 255)

dfll-multiply-factor

int

Determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency (0
- 65535)

dfll-src-gclk

string

Reference source clock selection from gclk generator

Default value: gclk0

Legal values: 'gclk0', 'gclk1', 'gclk2', 'gclk3', 'gclk4', 'gclk5', 'gclk6', 'gclk7', 'gclk8', 'gclk9', 'gclk10', 'gclk11'