microchip,sam-d5x-e5x-fdpll

Description

SAM_D5x_E5x FDPLL clock

Digital Phase Locked Loop (FDPLL), 96 MHz to 200 MHz output frequency from a 32 kHz to 3.2 MHz
reference clock.

Properties

Top level properties

These property descriptions apply to “microchip,sam-d5x-e5x-fdpll” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Child node properties

Name

Type

Details

subsystem

int

Clock subsystem

This property is required.

fdpll-on-demand-en

int

0: The oscillator is always on
1: The oscillator is running when a peripheral is requesting the oscillator to be used as a
clock source. The oscillator is not running if no peripheral is requesting the clock source.
Important: Initializing it with 1, along with clock enabled, can lead to indefinite wait
for the clock to be on, if there is no peripheral request for the clock in the sequence of
clock Initialization. If required, better to turn on the clock using API, instead of
enabling both during startup.

Legal values: 0, 1

fdpll-run-in-standby-en

int

0: The DPLLn is not running in standby sleep mode if no peripheral requests the clock.
1: The DPLLn is running in standby sleep mode.
If ONDEMAND is one, the DPLLn will be running when a peripheral is requesting the clock. If
ONDEMAND is false, the clock source will always be running in standby sleep mode.

Default value: 1

Legal values: 0, 1

fdpll-en

int

Oscillator Enable

Legal values: 0, 1

fdpll-divider-ratio-int

int

Set the integer part of the frequency multiplier. (0 - 4095)

fdpll-divider-ratio-frac

int

Set the fractional part of the frequency multiplier. (0 - 31)

fdpll-xosc-clock-divider

int

Set the XOSC clock division factor (0 - 2047)

fdpll-dco-en

int

DCO Filter Enable
0: to disable, 1: to enable

Legal values: 0, 1

fdpll-dco-filter-select

string

Sigma-Delta DCO Filter Selection, Bandwidth Fn (MHz)

Default value: 3.21mhz

Legal values: '3.21mhz', '1.6mhz', '1.1mhz', '0.8mhz', '0.64mhz', '0.55mhz', '0.45mhz', '0.4mhz'

fdpll-lock-bypass-en

int

Lock Bypass
0: to disable, 1: to enable

Legal values: 0, 1

fdpll-src

string

Reference source clock selection

Default value: xosc0

Legal values: 'gclk0', 'gclk1', 'gclk2', 'gclk3', 'gclk4', 'gclk5', 'gclk6', 'gclk7', 'gclk8', 'gclk9', 'gclk10', 'gclk11', 'xosc32k', 'xosc0', 'xosc1'

fdpll-wakeup-fast-en

int

Wake Up Fast
0: to disable, 1: to enable

Legal values: 0, 1

fdpll-pi-filter-type

string

Proportional Integral Filter Selection

Default value: 92.7khz-0.76damp

Legal values: '92.7khz-0.76damp', '131khz-1.08damp', '46.4khz-0.38damp', '65.6khz-0.54damp', '131khz-0.56damp', '185khz-0.79damp', '65.6khz-0.28damp', '92.7khz-0.39damp', '46.4khz-1.49damp', '65.6khz-2.11damp', '23.2khz-0.75damp', '32.8khz-1.06damp', '65.6khz-1.07damp', '92.7khz-1.51damp', '32.8khz-0.53damp', '46.4khz-0.75damp'