sifli,sf32lb-rcc-clk

Overview

Name:

sifli,sf32lb-rcc-clk

Vendor:

SiFli Technologies(Nanjing) Co., Ltd

Used in:

List of boards using this compatible

Driver:

drivers/clock_control/clock_control_sf32lb_rcc.c

Description

SiFli Reset and Clock Controller (RCC) is a multi-function peripheral in
charge of reset control and clock control for all SoC peripherals. This
binding represents the clock controller part. It is meant to be used as a
child node of the RCC node. This is due to the fact Zephyr does not allow
>1 device referencing to the same devicetree node (e.g. clock and reset
devices).

To specify the clocks in a peripheral, the standard clocks property needs
to be used, e.g.:

  usart1: serial@xxx {
      ...
      /* cell encodes RCC register offset and control bit position */
      clocks = <&rcc_clk SF32LB52X_CLOCK_USART1>;
      ...
  }

Predefined RCC clock cells are available in
include/zephyr/dts-bindings/clock/sf32lb{xxx}-clocks.h header files, where
{xxx} corresponds to the SoC series, e.g. sf32lb52x.

Properties

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

Name	Type	Details
#clock-cells	int	Number of items to expect in a Clock specifier This property is required. Constant value: 1
sifli,cfg	phandle	Phandle to the SiFli SF32LB System Configuration (HPSYS_CFG) This property is required.
sifli,pmuc	phandle	SiFli SF32LB PMUC node This property is required.
sifli,hdiv	int	Divider for HCLK (0-255). fHCLK = clk_hpsys / HDIV. This property is required.
sifli,pdiv1	int	Divider for PCLK1 (0-7). fPCLK1 = fHCLK / 2^PDIV1. This property is required.
sifli,pdiv2	int	Divider for PCLK2 (0-7). fPCLK2 = fHCLK / 2^PDIV2. This property is required.
sifli,sys-clk-src	string	Source used for the HPSYS system clock. When set to ``dll1`` the DLL1 child node must be enabled. Defaults to ``hrc48`` if not provided (reset default). Default value: hrc48 Legal values: 'hrc48', 'hxt48', 'lpclk', 'dll1'
sifli,peri-clk-src	string	Source used for the HPSYS peripheral clock domain. Defaults to ``hxt48`` if not provided (reset default). Default value: hxt48 Legal values: 'hrc48', 'hxt48'
sifli,mpi1-clk-src	string	Source used for the MPI1/QSPI clock tree. Selecting ``dll1`` or ``dll2`` requires the corresponding DLL child node to be enabled. Defaults to ``peri`` if not provided (reset default). Default value: peri Legal values: 'peri', 'dll1', 'dll2'
sifli,mpi2-clk-src	string	Source used for the MPI2/QSPI clock tree. Selecting ``dll1`` or ``dll2`` requires the corresponding DLL child node to be enabled. Defaults to ``peri`` if not provided (reset default). Default value: peri Legal values: 'peri', 'dll1', 'dll2'
sifli,usb-clk-src	string	Source used for the USB full-speed controller clock. Selecting ``dll2`` requires the DLL2 child node to be enabled. Defaults to ``sysclk`` if not provided (reset default). Default value: sysclk Legal values: 'sysclk', 'dll2'
sifli,usb-div	int	Divider applied to the selected USB clock source. The divided clock must be 60 MHz. For example, when ``clk_dll2`` runs at 240 MHz the divider must be ``4`` (reset default). Default value: 4

Specifier cell names

• clock cells: id