st,stm32c5-rcc

Description

STM32C5 RCC (Reset and Clock controller).

This node is in charge of system clock ('SYSCLK') source selection and controlling
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.

It also allows the configuration of the different PSI clocks (PSIS, PSIK, PSIDIV3).

When using any of the PSI clocks, it is necessary to configure the PSI target
frequency (PSIFREQ register) and the PSI source clock (PSIREFSRC register).
From these two values, the value of the PSIREF register is automatically calculated.

Refer to st,stm32-rcc.yaml for more details.

Properties

Properties not inherited from the base binding file.

Name

Type

Details

apb3-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

st,psi-frequency

int

PSI target frequency configuration, in MHz.

Legal values: 100, 144, 160

st,psi-source

string

Clock source for PSI clock.

Legal values: HSE, LSE, HSIDIV18

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

Constant value: 2

clock-frequency

int

default frequency in Hz for clock output

This property is required.

ahb-prescaler

int

AHB prescaler. Defines actual core clock frequency (HCLK)
based on system frequency input.
The HCLK clocks CPU, AHB, memories and DMA.

This property is required.

Legal values: 1, 2, 4, 8, 16, 64, 128, 256, 512

apb1-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

apb2-prescaler

int

This property is required.

Legal values: 1, 2, 4, 8, 16

Specifier cell names

  • clock cells: bus, bits